xref: /rk3399_ARM-atf/plat/mediatek/drivers/dfd/dfd.c (revision 7079a942bd9705fd9e0cd220324f7dfd9c53dcad)
1*7079a942SFengquan Chen /*
2*7079a942SFengquan Chen  * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3*7079a942SFengquan Chen  *
4*7079a942SFengquan Chen  * SPDX-License-Identifier: BSD-3-Clause
5*7079a942SFengquan Chen  */
6*7079a942SFengquan Chen #include <arch_helpers.h>
7*7079a942SFengquan Chen #include <common/debug.h>
8*7079a942SFengquan Chen #include <lib/mmio.h>
9*7079a942SFengquan Chen #include <dfd.h>
10*7079a942SFengquan Chen #include <mtk_sip_svc.h>
11*7079a942SFengquan Chen #include <plat_dfd.h>
12*7079a942SFengquan Chen 
13*7079a942SFengquan Chen static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1,
14*7079a942SFengquan Chen 				       u_register_t arg2, u_register_t arg3,
15*7079a942SFengquan Chen 				       void *handle, struct smccc_res *smccc_ret)
16*7079a942SFengquan Chen {
17*7079a942SFengquan Chen 	int ret = MTK_SIP_E_SUCCESS;
18*7079a942SFengquan Chen 
19*7079a942SFengquan Chen 	switch (arg0) {
20*7079a942SFengquan Chen 	case PLAT_MTK_DFD_SETUP_MAGIC:
21*7079a942SFengquan Chen 		INFO("[%s] DFD setup call from kernel\n", __func__);
22*7079a942SFengquan Chen 		dfd_setup(arg1, arg2, arg3);
23*7079a942SFengquan Chen 		break;
24*7079a942SFengquan Chen 	case PLAT_MTK_DFD_READ_MAGIC:
25*7079a942SFengquan Chen 		/* only allow to access DFD register base + 0x200 */
26*7079a942SFengquan Chen 		if (arg1 <= 0x200) {
27*7079a942SFengquan Chen 			ret = mmio_read_32(MISC1_CFG_BASE + arg1);
28*7079a942SFengquan Chen 		}
29*7079a942SFengquan Chen 		break;
30*7079a942SFengquan Chen 	case PLAT_MTK_DFD_WRITE_MAGIC:
31*7079a942SFengquan Chen 		/* only allow to access DFD register base + 0x200 */
32*7079a942SFengquan Chen 		if (arg1 <= 0x200) {
33*7079a942SFengquan Chen 			sync_writel(MISC1_CFG_BASE + arg1, arg2);
34*7079a942SFengquan Chen 		}
35*7079a942SFengquan Chen 		break;
36*7079a942SFengquan Chen 	default:
37*7079a942SFengquan Chen 		ret = MTK_SIP_E_INVALID_PARAM;
38*7079a942SFengquan Chen 		break;
39*7079a942SFengquan Chen 	}
40*7079a942SFengquan Chen 
41*7079a942SFengquan Chen 	return ret;
42*7079a942SFengquan Chen }
43*7079a942SFengquan Chen DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_DFD, dfd_smc_dispatcher);
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