1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 #include <lib/utils_def.h> 9 #include <mtk_dcm_utils.h> 10 11 #define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK BIT(17) 12 #define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | BIT(16) | BIT(17) | \ 13 BIT(18) | BIT(21)) 14 #define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | BIT(16) | BIT(17) | BIT(18)) 15 #define MP_CPUSYS_TOP_ADB_DCM_REG0_ON BIT(17) 16 #define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | BIT(16) | BIT(17) | \ 17 BIT(18) | BIT(21)) 18 #define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | BIT(16) | BIT(17) | BIT(18)) 19 #define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF (0x0 << 17) 20 #define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | (0x0 << 16) | \ 21 (0x0 << 17) | (0x0 << 18) | \ 22 (0x0 << 21)) 23 #define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | (0x0 << 16) | \ 24 (0x0 << 17) | (0x0 << 18)) 25 26 bool dcm_mp_cpusys_top_adb_dcm_is_on(void) 27 { 28 bool ret = true; 29 30 ret &= dcm_check_state(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, 31 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, 32 MP_CPUSYS_TOP_ADB_DCM_REG0_ON); 33 ret &= dcm_check_state(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, 34 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, 35 MP_CPUSYS_TOP_ADB_DCM_REG1_ON); 36 ret &= dcm_check_state(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 37 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, 38 MP_CPUSYS_TOP_ADB_DCM_REG2_ON); 39 40 return ret; 41 } 42 43 void dcm_mp_cpusys_top_adb_dcm(bool on) 44 { 45 if (on) { 46 /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */ 47 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, 48 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, 49 MP_CPUSYS_TOP_ADB_DCM_REG0_ON); 50 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, 51 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, 52 MP_CPUSYS_TOP_ADB_DCM_REG1_ON); 53 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 54 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, 55 MP_CPUSYS_TOP_ADB_DCM_REG2_ON); 56 } else { 57 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */ 58 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, 59 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK, 60 MP_CPUSYS_TOP_ADB_DCM_REG0_OFF); 61 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, 62 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK, 63 MP_CPUSYS_TOP_ADB_DCM_REG1_OFF); 64 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 65 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK, 66 MP_CPUSYS_TOP_ADB_DCM_REG2_OFF); 67 } 68 } 69 70 #define MP_CPUSYS_TOP_APB_DCM_REG0_MASK BIT(5) 71 #define MP_CPUSYS_TOP_APB_DCM_REG1_MASK BIT(8) 72 #define MP_CPUSYS_TOP_APB_DCM_REG2_MASK BIT(16) 73 #define MP_CPUSYS_TOP_APB_DCM_REG0_ON BIT(5) 74 #define MP_CPUSYS_TOP_APB_DCM_REG1_ON BIT(8) 75 #define MP_CPUSYS_TOP_APB_DCM_REG2_ON BIT(16) 76 #define MP_CPUSYS_TOP_APB_DCM_REG0_OFF (0x0 << 5) 77 #define MP_CPUSYS_TOP_APB_DCM_REG1_OFF (0x0 << 8) 78 #define MP_CPUSYS_TOP_APB_DCM_REG2_OFF (0x0 << 16) 79 80 bool dcm_mp_cpusys_top_apb_dcm_is_on(void) 81 { 82 bool ret = true; 83 84 ret &= dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 85 MP_CPUSYS_TOP_APB_DCM_REG0_MASK, 86 MP_CPUSYS_TOP_APB_DCM_REG0_ON); 87 ret &= dcm_check_state(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 88 MP_CPUSYS_TOP_APB_DCM_REG1_MASK, 89 MP_CPUSYS_TOP_APB_DCM_REG1_ON); 90 ret &= dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG0, 91 MP_CPUSYS_TOP_APB_DCM_REG2_MASK, 92 MP_CPUSYS_TOP_APB_DCM_REG2_ON); 93 94 return ret; 95 } 96 97 void dcm_mp_cpusys_top_apb_dcm(bool on) 98 { 99 if (on) { 100 /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */ 101 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 102 MP_CPUSYS_TOP_APB_DCM_REG0_MASK, 103 MP_CPUSYS_TOP_APB_DCM_REG0_ON); 104 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 105 MP_CPUSYS_TOP_APB_DCM_REG1_MASK, 106 MP_CPUSYS_TOP_APB_DCM_REG1_ON); 107 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, 108 MP_CPUSYS_TOP_APB_DCM_REG2_MASK, 109 MP_CPUSYS_TOP_APB_DCM_REG2_ON); 110 } else { 111 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */ 112 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 113 MP_CPUSYS_TOP_APB_DCM_REG0_MASK, 114 MP_CPUSYS_TOP_APB_DCM_REG0_OFF); 115 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, 116 MP_CPUSYS_TOP_APB_DCM_REG1_MASK, 117 MP_CPUSYS_TOP_APB_DCM_REG1_OFF); 118 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, 119 MP_CPUSYS_TOP_APB_DCM_REG2_MASK, 120 MP_CPUSYS_TOP_APB_DCM_REG2_OFF); 121 } 122 } 123 124 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11) | BIT(24) | BIT(25)) 125 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | BIT(24) | BIT(25)) 126 #define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11) | \ 127 (0x0 << 24) | \ 128 (0x0 << 25)) 129 130 bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void) 131 { 132 return dcm_check_state(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 133 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, 134 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); 135 } 136 137 void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on) 138 { 139 if (on) { 140 /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ 141 mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 142 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, 143 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON); 144 } else { 145 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */ 146 mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 147 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK, 148 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF); 149 } 150 } 151 152 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK BIT(0) 153 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON BIT(0) 154 #define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF (0x0 << 0) 155 156 bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void) 157 { 158 return dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG7, 159 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, 160 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); 161 } 162 163 void dcm_mp_cpusys_top_core_stall_dcm(bool on) 164 { 165 if (on) { 166 /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */ 167 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, 168 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, 169 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON); 170 } else { 171 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */ 172 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, 173 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK, 174 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF); 175 } 176 } 177 178 #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK (0xffff << 0) 179 #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON (0xffff << 0) 180 #define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF (0x0 << 0) 181 182 bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void) 183 { 184 return dcm_check_state(MP_CPUSYS_TOP_MCSIC_DCM0, 185 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, 186 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); 187 } 188 189 void dcm_mp_cpusys_top_cpubiu_dcm(bool on) 190 { 191 if (on) { 192 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */ 193 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, 194 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, 195 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON); 196 } else { 197 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */ 198 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0, 199 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK, 200 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF); 201 } 202 } 203 204 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(24) | BIT(25)) 205 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(24) | BIT(25)) 206 #define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 24) | (0x0 << 25)) 207 208 bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void) 209 { 210 return dcm_check_state(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, 211 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, 212 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); 213 } 214 215 void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on) 216 { 217 if (on) { 218 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ 219 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, 220 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, 221 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON); 222 } else { 223 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */ 224 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0, 225 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK, 226 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF); 227 } 228 } 229 230 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(24) | BIT(25)) 231 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(24) | BIT(25)) 232 #define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 24) | (0x0 << 25)) 233 234 bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void) 235 { 236 return dcm_check_state(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, 237 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, 238 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); 239 } 240 241 void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on) 242 { 243 if (on) { 244 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ 245 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, 246 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, 247 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON); 248 } else { 249 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */ 250 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, 251 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK, 252 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF); 253 } 254 } 255 256 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK BIT(4) 257 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON BIT(4) 258 #define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF (0x0 << 4) 259 260 bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void) 261 { 262 return dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG7, 263 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, 264 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); 265 } 266 267 void dcm_mp_cpusys_top_fcm_stall_dcm(bool on) 268 { 269 if (on) { 270 /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */ 271 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, 272 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, 273 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON); 274 } else { 275 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */ 276 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7, 277 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK, 278 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF); 279 } 280 } 281 282 #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK BIT(31) 283 #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON BIT(31) 284 #define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF (0x0U << 31) 285 286 bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void) 287 { 288 return dcm_check_state(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 289 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, 290 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); 291 } 292 293 void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on) 294 { 295 if (on) { 296 /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ 297 mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 298 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, 299 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON); 300 } else { 301 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */ 302 mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG, 303 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK, 304 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF); 305 } 306 } 307 308 #define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | BIT(4)) 309 #define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | BIT(4)) 310 #define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | (0x0 << 4)) 311 312 bool dcm_mp_cpusys_top_misc_dcm_is_on(void) 313 { 314 return dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 315 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, 316 MP_CPUSYS_TOP_MISC_DCM_REG0_ON); 317 } 318 319 void dcm_mp_cpusys_top_misc_dcm(bool on) 320 { 321 if (on) { 322 /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */ 323 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 324 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, 325 MP_CPUSYS_TOP_MISC_DCM_REG0_ON); 326 } else { 327 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */ 328 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 329 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK, 330 MP_CPUSYS_TOP_MISC_DCM_REG0_OFF); 331 } 332 } 333 334 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK BIT(3) 335 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 336 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON BIT(3) 337 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 338 #define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3)) 339 #define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | (0x0 << 1) | \ 340 (0x0 << 2) | (0x0 << 3)) 341 342 bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void) 343 { 344 bool ret = true; 345 346 ret &= dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 347 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, 348 MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); 349 ret &= dcm_check_state(MP_CPUSYS_TOP_MP0_DCM_CFG0, 350 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, 351 MP_CPUSYS_TOP_MP0_QDCM_REG1_ON); 352 353 return ret; 354 } 355 356 void dcm_mp_cpusys_top_mp0_qdcm(bool on) 357 { 358 if (on) { 359 /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */ 360 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 361 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, 362 MP_CPUSYS_TOP_MP0_QDCM_REG0_ON); 363 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, 364 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, 365 MP_CPUSYS_TOP_MP0_QDCM_REG1_ON); 366 } else { 367 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */ 368 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, 369 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK, 370 MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF); 371 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, 372 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK, 373 MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF); 374 } 375 } 376 377 #define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 378 #define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 379 #define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | (0x0 << 1) | \ 380 (0x0 << 2) | (0x0 << 3)) 381 382 bool dcm_cpccfg_reg_emi_wfifo_is_on(void) 383 { 384 return dcm_check_state(CPCCFG_REG_EMI_WFIFO, 385 CPCCFG_REG_EMI_WFIFO_REG0_MASK, 386 CPCCFG_REG_EMI_WFIFO_REG0_ON); 387 } 388 389 void dcm_cpccfg_reg_emi_wfifo(bool on) 390 { 391 if (on) { 392 /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */ 393 mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, 394 CPCCFG_REG_EMI_WFIFO_REG0_MASK, 395 CPCCFG_REG_EMI_WFIFO_REG0_ON); 396 } else { 397 /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */ 398 mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO, 399 CPCCFG_REG_EMI_WFIFO_REG0_MASK, 400 CPCCFG_REG_EMI_WFIFO_REG0_OFF); 401 } 402 } 403