1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_PPU_H 8 #define MT_PPU_H 9 10 #include <lib/mmio.h> 11 #include "mt_cpu_pm.h" 12 13 /* PPU PWPR definition */ 14 #define PPU_PWPR_MASK 0xF 15 #define PPU_PWPR_MODE_MASK 0x1 16 #define PPU_PWPR_OFF 0 17 #define PPU_PWPR_MEM_RET 2 18 #define PPU_PWPR_FULL_RET 5 19 #define PPU_PWPR_MEM_OFF 6 20 #define PPU_PWPR_FUN_RET 7 21 #define PPU_PWPR_ON 8 22 #define PPU_PWPR_WARM_RESET 10 23 #define PPU_PWPR_DYNAMIC_MODE BIT(8) 24 25 #define PPU_PWPR_OP_MASK 0xF0000 26 #define PPU_PWPR_OP_DYNAMIC_MODE BIT(24) 27 #define PPU_PWPR_OP_MODE(_policy) (((_policy) << 16) & PPU_PWPR_OP_MASK) 28 #define PPU_PWPR_OP_ONE_SLICE_SF_ONLY 0 29 #define PPU_PWPR_OP_ONE_SLICE_HALF_DRAM 1 30 #define PPU_PWPR_OP_ONE_SLICE_FULL_DRAM 3 31 #define PPU_PWPR_OP_ALL_SLICE_SF_ONLY 4 32 #define PPU_PWPR_OP_ALL_SLICE_HALF_DRAM 5 33 #define PPU_PWPR_OP_ALL_SLICE_FULL_DRAM 7 34 35 #define DSU_PPU_PWPR_OP_MODE_DEF (PPU_PWPR_OP_ONE_SLICE_HALF_DRAM) 36 37 /* PPU PWSR definition */ 38 #define PPU_PWSR_STATE_ON BIT(3) 39 40 #ifdef CPU_PM_ACP_FSM 41 #define PPU_PWSR_OP_STATUS 0x30000 42 #define PPU_OP_ST_SF_ONLY 0x0 43 #endif /* CPU_PM_ACP_FSM */ 44 45 #define MT_PPU_DCDR0 0x00606060 46 #define MT_PPU_DCDR1 0x00006060 47 48 void mt_smp_ppu_pwr_set(struct ppu_pwr_ctrl *ctrl, 49 unsigned int mode, 50 unsigned int policy); 51 52 void mt_smp_ppu_op_set(struct ppu_pwr_ctrl *ctrl, 53 unsigned int mode, 54 unsigned int policy); 55 56 void mt_smp_ppu_pwr_dynamic_set(struct ppu_pwr_ctrl *ctrl, 57 unsigned int policy); 58 59 void mt_smp_ppu_pwr_static_set(struct ppu_pwr_ctrl *ctrl, 60 unsigned int policy); 61 62 void mt_smp_ppu_set(struct ppu_pwr_ctrl *ctrl, 63 unsigned int op_mode, 64 unsigned int policy, 65 unsigned int pwr_mode, 66 unsigned int pwr_policy); 67 68 #endif /* MT_PPU_H */ 69