1*75530ee2SKai Liang /* 2*75530ee2SKai Liang * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3*75530ee2SKai Liang * 4*75530ee2SKai Liang * SPDX-License-Identifier: BSD-3-Clause 5*75530ee2SKai Liang */ 6*75530ee2SKai Liang 7*75530ee2SKai Liang #ifndef MT_PPU_H 8*75530ee2SKai Liang #define MT_PPU_H 9*75530ee2SKai Liang 10*75530ee2SKai Liang #include <lib/mmio.h> 11*75530ee2SKai Liang #include "mt_cpu_pm.h" 12*75530ee2SKai Liang 13*75530ee2SKai Liang /* PPU PWPR definition */ 14*75530ee2SKai Liang #define PPU_PWPR_MASK 0xF 15*75530ee2SKai Liang #define PPU_PWPR_MODE_MASK 0x1 16*75530ee2SKai Liang #define PPU_PWPR_OFF 0 17*75530ee2SKai Liang #define PPU_PWPR_MEM_RET 2 18*75530ee2SKai Liang #define PPU_PWPR_FULL_RET 5 19*75530ee2SKai Liang #define PPU_PWPR_MEM_OFF 6 20*75530ee2SKai Liang #define PPU_PWPR_FUN_RET 7 21*75530ee2SKai Liang #define PPU_PWPR_ON 8 22*75530ee2SKai Liang #define PPU_PWPR_WARM_RESET 10 23*75530ee2SKai Liang #define PPU_PWPR_DYNAMIC_MODE BIT(8) 24*75530ee2SKai Liang 25*75530ee2SKai Liang #define PPU_PWPR_OP_MASK 0xF0000 26*75530ee2SKai Liang #define PPU_PWPR_OP_DYNAMIC_MODE BIT(24) 27*75530ee2SKai Liang #define PPU_PWPR_OP_MODE(_policy) (((_policy) << 16) & PPU_PWPR_OP_MASK) 28*75530ee2SKai Liang #define PPU_PWPR_OP_ONE_SLICE_SF_ONLY 0 29*75530ee2SKai Liang #define PPU_PWPR_OP_ONE_SLICE_HALF_DRAM 1 30*75530ee2SKai Liang #define PPU_PWPR_OP_ONE_SLICE_FULL_DRAM 3 31*75530ee2SKai Liang #define PPU_PWPR_OP_ALL_SLICE_SF_ONLY 4 32*75530ee2SKai Liang #define PPU_PWPR_OP_ALL_SLICE_HALF_DRAM 5 33*75530ee2SKai Liang #define PPU_PWPR_OP_ALL_SLICE_FULL_DRAM 7 34*75530ee2SKai Liang 35*75530ee2SKai Liang #define DSU_PPU_PWPR_OP_MODE_DEF (PPU_PWPR_OP_ONE_SLICE_HALF_DRAM) 36*75530ee2SKai Liang 37*75530ee2SKai Liang /* PPU PWSR definition */ 38*75530ee2SKai Liang #define PPU_PWSR_STATE_ON BIT(3) 39*75530ee2SKai Liang 40*75530ee2SKai Liang #ifdef CPU_PM_ACP_FSM 41*75530ee2SKai Liang #define PPU_PWSR_OP_STATUS 0x30000 42*75530ee2SKai Liang #define PPU_OP_ST_SF_ONLY 0x0 43*75530ee2SKai Liang #endif /* CPU_PM_ACP_FSM */ 44*75530ee2SKai Liang 45*75530ee2SKai Liang #define MT_PPU_DCDR0 0x00606060 46*75530ee2SKai Liang #define MT_PPU_DCDR1 0x00006060 47*75530ee2SKai Liang 48*75530ee2SKai Liang void mt_smp_ppu_pwr_set(struct ppu_pwr_ctrl *ctrl, 49*75530ee2SKai Liang unsigned int mode, 50*75530ee2SKai Liang unsigned int policy); 51*75530ee2SKai Liang 52*75530ee2SKai Liang void mt_smp_ppu_op_set(struct ppu_pwr_ctrl *ctrl, 53*75530ee2SKai Liang unsigned int mode, 54*75530ee2SKai Liang unsigned int policy); 55*75530ee2SKai Liang 56*75530ee2SKai Liang void mt_smp_ppu_pwr_dynamic_set(struct ppu_pwr_ctrl *ctrl, 57*75530ee2SKai Liang unsigned int policy); 58*75530ee2SKai Liang 59*75530ee2SKai Liang void mt_smp_ppu_pwr_static_set(struct ppu_pwr_ctrl *ctrl, 60*75530ee2SKai Liang unsigned int policy); 61*75530ee2SKai Liang 62*75530ee2SKai Liang void mt_smp_ppu_set(struct ppu_pwr_ctrl *ctrl, 63*75530ee2SKai Liang unsigned int op_mode, 64*75530ee2SKai Liang unsigned int policy, 65*75530ee2SKai Liang unsigned int pwr_mode, 66*75530ee2SKai Liang unsigned int pwr_policy); 67*75530ee2SKai Liang 68*75530ee2SKai Liang #endif /* MT_PPU_H */ 69