xref: /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_ppu.c (revision 06f3c7058c42a9f1a9f7df75ea2de71a000855e8)
1 /*
2  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include "mt_ppu.h"
8 
9 #define MTK_PPU_PWR_DYNAMIC_POLICY_SET(_ctrl, _policy) \
10 	mmio_clrsetbits_32(_ctrl->ppu_pwpr, \
11 			   PPU_PWPR_MASK, \
12 			   PPU_PWPR_DYNAMIC_MODE | ((_policy) & PPU_PWPR_MASK))
13 
14 #define MTK_PPU_PWR_STATIC_POLICY_SET(_ctrl, _policy) \
15 	mmio_clrsetbits_32(_ctrl->ppu_pwpr, \
16 			   PPU_PWPR_MASK | PPU_PWPR_DYNAMIC_MODE, \
17 			   ((_policy) & PPU_PWPR_MASK))
18 
19 void mt_smp_ppu_pwr_dynamic_set(struct ppu_pwr_ctrl *ctrl,
20 				unsigned int policy)
21 {
22 	CPU_PM_ASSERT(ctrl);
23 	MTK_PPU_PWR_DYNAMIC_POLICY_SET(ctrl, policy);
24 	dmbsy();
25 }
26 
27 void mt_smp_ppu_pwr_static_set(struct ppu_pwr_ctrl *ctrl,
28 			       unsigned int policy)
29 {
30 	CPU_PM_ASSERT(ctrl);
31 	MTK_PPU_PWR_STATIC_POLICY_SET(ctrl, policy);
32 	dmbsy();
33 }
34 
35 void mt_smp_ppu_pwr_set(struct ppu_pwr_ctrl *ctrl,
36 			unsigned int mode,
37 			unsigned int policy)
38 {
39 	CPU_PM_ASSERT(ctrl);
40 	if (mode & PPU_PWPR_DYNAMIC_MODE)
41 		MTK_PPU_PWR_DYNAMIC_POLICY_SET(ctrl, policy);
42 	else
43 		MTK_PPU_PWR_STATIC_POLICY_SET(ctrl, policy);
44 	mmio_write_32(ctrl->ppu_dcdr0, MT_PPU_DCDR0);
45 	mmio_write_32(ctrl->ppu_dcdr1, MT_PPU_DCDR1);
46 	dsbsy();
47 }
48 
49 void mt_smp_ppu_op_set(struct ppu_pwr_ctrl *ctrl,
50 		       unsigned int mode,
51 		       unsigned int policy)
52 {
53 	unsigned int val;
54 
55 	CPU_PM_ASSERT(ctrl);
56 
57 	val = mmio_read_32(ctrl->ppu_pwpr);
58 	val &= ~(PPU_PWPR_OP_MASK | PPU_PWPR_OP_DYNAMIC_MODE);
59 
60 	val |= PPU_PWPR_OP_MODE(policy);
61 	if (mode & PPU_PWPR_OP_DYNAMIC_MODE)
62 		val |= PPU_PWPR_OP_DYNAMIC_MODE;
63 
64 	mmio_write_32(ctrl->ppu_pwpr, val);
65 	dsbsy();
66 }
67 
68 void mt_smp_ppu_set(struct ppu_pwr_ctrl *ctrl,
69 		    unsigned int op_mode,
70 		    unsigned int policy,
71 		    unsigned int pwr_mode,
72 		    unsigned int pwr_policy)
73 {
74 	unsigned int val;
75 
76 	CPU_PM_ASSERT(ctrl);
77 	val = mmio_read_32(ctrl->ppu_pwpr);
78 
79 	if (op_mode & PPU_PWPR_OP_DYNAMIC_MODE)
80 		val |= (PPU_PWPR_OP_DYNAMIC_MODE |
81 		       PPU_PWPR_OP_MODE(policy));
82 	else
83 		val |= PPU_PWPR_OP_MODE(policy);
84 
85 	if (pwr_mode & PPU_PWPR_DYNAMIC_MODE) {
86 		val &= ~(PPU_PWPR_MASK);
87 		val |= (PPU_PWPR_DYNAMIC_MODE | (pwr_policy & PPU_PWPR_MASK));
88 	} else {
89 		val &= ~(PPU_PWPR_MASK | PPU_PWPR_DYNAMIC_MODE);
90 		val |= (pwr_policy & PPU_PWPR_MASK);
91 	}
92 	mmio_write_32(ctrl->ppu_pwpr, val);
93 	dsbsy();
94 }
95