xref: /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.h (revision 52e486f6a6192bd18d36cdcbc35c59092eefc810)
1 /*
2  * Copyright (c) 2024, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef APUSYS_SECURITY_CTRL_PLAT_H
8 #define APUSYS_SECURITY_CTRL_PLAT_H
9 
10 #include <lib/utils_def.h>
11 #include <platform_def.h>
12 
13 #define SEC_CTRL_SOC2APU_SET1_0		(APU_SEC_CON + 0xC)
14 #define SEC_CTRL_SOC2APU_SET1_1		(APU_SEC_CON + 0x10)
15 #define SEC_CTRL_SIDE_BAND		(APU_SEC_CON + 0x24)
16 
17 #define SEC_CTRL_REG_DOMAIN_NUM		(8)
18 #define SEC_CTRL_DOMAIN_REMAP_SEL	BIT(6)
19 #define SEC_CTRL_DOMAIN_MASK		(0xF)
20 #define SEC_CTRL_NS_MASK		(0x1)
21 
22 #define SEC_CTRL_NARE_DOMAIN		(5)
23 #define SEC_CTRL_NARE_NS		(0)
24 #define SEC_CTRL_NARE_DOMAIN_SHF	(0)
25 #define SEC_CTRL_NARE_NS_SHF		(4)
26 
27 #define SEC_CTRL_SARE0_DOMAIN		(5)
28 #define SEC_CTRL_SARE0_NS		(0)
29 #define SEC_CTRL_SARE0_DOMAIN_SHF	(5)
30 #define SEC_CTRL_SARE0_NS_SHF		(9)
31 
32 #define SEC_CTRL_SARE1_DOMAIN		(5)
33 #define SEC_CTRL_SARE1_NS		(0)
34 #define SEC_CTRL_SARE1_DOMAIN_SHF	(10)
35 #define SEC_CTRL_SARE1_NS_SHF		(14)
36 
37 #define REG_DOMAIN_BITS		(4)
38 
39 #define D0_REMAP_DOMAIN		(0)
40 #define D1_REMAP_DOMAIN		(1)
41 #define D2_REMAP_DOMAIN		(2)
42 #define D3_REMAP_DOMAIN		(3)
43 #define D4_REMAP_DOMAIN		(4)
44 #define D5_REMAP_DOMAIN		(6)
45 #define D6_REMAP_DOMAIN		(6)
46 #define D7_REMAP_DOMAIN		(6)
47 #define D8_REMAP_DOMAIN		(8)
48 #define D9_REMAP_DOMAIN		(9)
49 #define D10_REMAP_DOMAIN	(10)
50 #define D11_REMAP_DOMAIN	(11)
51 #define D12_REMAP_DOMAIN	(12)
52 #define D13_REMAP_DOMAIN	(13)
53 #define D14_REMAP_DOMAIN	(6)
54 #define D15_REMAP_DOMAIN	(15)
55 
56 void apusys_security_ctrl_init(void);
57 int apusys_plat_setup_sec_mem(void);
58 
59 #endif /* APUSYS_SECURITY_CTRL_PLAT_H */
60