xref: /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c (revision 9059a375eeb20c08cdcd5e604b9fd68b47a31e7e)
1 /*
2  * Copyright (c) 2024, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <lib/mmio.h>
8 
9 #include <apusys_security_ctrl_plat.h>
10 
11 #define bits_clr(x, m, o)	(x & (~(m << o)))
12 #define bits_set(x, v, m, o)	((bits_clr(x, m, o)) | ((v & m) << o))
13 
14 static void sec_sideband_init(void)
15 {
16 	uint32_t value = mmio_read_32(SEC_CTRL_SIDE_BAND);
17 
18 	value = bits_set(value, SEC_CTRL_NARE_DOMAIN, SEC_CTRL_DOMAIN_MASK,
19 			 SEC_CTRL_NARE_DOMAIN_SHF);
20 	value = bits_set(value, SEC_CTRL_NARE_NS, SEC_CTRL_NS_MASK, SEC_CTRL_NARE_NS_SHF);
21 	value = bits_set(value, SEC_CTRL_SARE0_DOMAIN, SEC_CTRL_DOMAIN_MASK,
22 			 SEC_CTRL_SARE0_DOMAIN_SHF);
23 	value = bits_set(value, SEC_CTRL_SARE0_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE0_NS_SHF);
24 	value = bits_set(value, SEC_CTRL_SARE1_DOMAIN, SEC_CTRL_DOMAIN_MASK,
25 			 SEC_CTRL_SARE1_DOMAIN_SHF);
26 	value = bits_set(value, SEC_CTRL_SARE1_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE1_NS_SHF);
27 
28 	mmio_write_32(SEC_CTRL_SIDE_BAND, value);
29 }
30 
31 static void domain_remap_init(void)
32 {
33 	const uint32_t remap_domains[] = {
34 		D0_REMAP_DOMAIN,  D1_REMAP_DOMAIN,  D2_REMAP_DOMAIN,  D3_REMAP_DOMAIN,
35 		D4_REMAP_DOMAIN,  D5_REMAP_DOMAIN,  D6_REMAP_DOMAIN,  D7_REMAP_DOMAIN,
36 		D8_REMAP_DOMAIN,  D9_REMAP_DOMAIN,  D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
37 		D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN,
38 	};
39 	uint32_t lower_domain = 0;
40 	uint32_t higher_domain = 0;
41 	int i;
42 
43 	for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
44 		if (i < SEC_CTRL_REG_DOMAIN_NUM)
45 			lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
46 		else
47 			higher_domain |= (remap_domains[i] <<
48 					  ((i - SEC_CTRL_REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
49 	}
50 
51 	mmio_write_32(SEC_CTRL_SOC2APU_SET1_0, lower_domain);
52 	mmio_write_32(SEC_CTRL_SOC2APU_SET1_1, higher_domain);
53 	mmio_setbits_32(APU_SEC_CON, SEC_CTRL_DOMAIN_REMAP_SEL);
54 }
55 
56 void apusys_security_ctrl_init(void)
57 {
58 	domain_remap_init();
59 	sec_sideband_init();
60 }
61