xref: /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c (revision 04cf04c72d403e0c057505882fac9002d39d4102)
1 /*
2  * Copyright (c) 2024-2025, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #define ENABLE_SMPU_PROTECT	(1)
8 
9 #include <common/debug.h>
10 #include <lib/mmio.h>
11 
12 #include <apusys_security_ctrl_plat.h>
13 #include <mtk_bl31_interface.h>
14 
15 #define APUSYS_SEC_FW_EMI_REGION	(23)
16 
17 #define bits_clr(x, m, o)	(x & (~(m << o)))
18 #define bits_set(x, v, m, o)	((bits_clr(x, m, o)) | ((v & m) << o))
19 
20 static void sec_sideband_init(void)
21 {
22 	uint32_t value = mmio_read_32(SEC_CTRL_SIDE_BAND);
23 
24 	value = bits_set(value, SEC_CTRL_NARE_DOMAIN, SEC_CTRL_DOMAIN_MASK,
25 			 SEC_CTRL_NARE_DOMAIN_SHF);
26 	value = bits_set(value, SEC_CTRL_NARE_NS, SEC_CTRL_NS_MASK, SEC_CTRL_NARE_NS_SHF);
27 	value = bits_set(value, SEC_CTRL_SARE0_DOMAIN, SEC_CTRL_DOMAIN_MASK,
28 			 SEC_CTRL_SARE0_DOMAIN_SHF);
29 	value = bits_set(value, SEC_CTRL_SARE0_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE0_NS_SHF);
30 	value = bits_set(value, SEC_CTRL_SARE1_DOMAIN, SEC_CTRL_DOMAIN_MASK,
31 			 SEC_CTRL_SARE1_DOMAIN_SHF);
32 	value = bits_set(value, SEC_CTRL_SARE1_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE1_NS_SHF);
33 
34 	mmio_write_32(SEC_CTRL_SIDE_BAND, value);
35 }
36 
37 static void domain_remap_init(void)
38 {
39 	const uint32_t remap_domains[] = {
40 		D0_REMAP_DOMAIN,  D1_REMAP_DOMAIN,  D2_REMAP_DOMAIN,  D3_REMAP_DOMAIN,
41 		D4_REMAP_DOMAIN,  D5_REMAP_DOMAIN,  D6_REMAP_DOMAIN,  D7_REMAP_DOMAIN,
42 		D8_REMAP_DOMAIN,  D9_REMAP_DOMAIN,  D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
43 		D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN,
44 	};
45 	uint32_t lower_domain = 0;
46 	uint32_t higher_domain = 0;
47 	int i;
48 
49 	for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
50 		if (i < SEC_CTRL_REG_DOMAIN_NUM)
51 			lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
52 		else
53 			higher_domain |= (remap_domains[i] <<
54 					  ((i - SEC_CTRL_REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
55 	}
56 
57 	mmio_write_32(SEC_CTRL_SOC2APU_SET1_0, lower_domain);
58 	mmio_write_32(SEC_CTRL_SOC2APU_SET1_1, higher_domain);
59 	mmio_setbits_32(APU_SEC_CON, SEC_CTRL_DOMAIN_REMAP_SEL);
60 }
61 
62 void apusys_security_ctrl_init(void)
63 {
64 	domain_remap_init();
65 	sec_sideband_init();
66 }
67 
68 int apusys_plat_setup_sec_mem(void)
69 {
70 #if ENABLE_SMPU_PROTECT
71 	return emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
72 				      (APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >>
73 				      EMI_MPU_ALIGN_BITS,
74 				      APUSYS_SEC_FW_EMI_REGION);
75 #else
76 	INFO("%s: Bypass SMPU protection setup.\n", __func__);
77 	return 0;
78 #endif
79 }
80