1 /* 2 * Copyright (c) 2024, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef APUSYS_RV_PWR_CTL_H 8 #define APUSYS_RV_PWR_CTL_H 9 10 #include <platform_def.h> 11 12 #include "apusys_rv.h" 13 14 #define SUPPORT_APU_CLEAR_MBOX_DUMMY (1) 15 16 enum apu_hw_sem_sys_id { 17 APU_HW_SEM_SYS_APU = 0UL, /* mbox0 */ 18 APU_HW_SEM_SYS_GZ = 1UL, /* mbox1 */ 19 APU_HW_SEM_SYS_SCP = 3UL, /* mbox3 */ 20 APU_HW_SEM_SYS_APMCU = 11UL, /* mbox11 */ 21 }; 22 23 int apusys_rv_pwr_ctrl(enum APU_PWR_OP op); 24 int rv_iommu_hw_sem_unlock(void); 25 int rv_iommu_hw_sem_trylock(void); 26 int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout, 27 uint8_t bypass); 28 29 #define HW_SEM_TIMEOUT (300) /* 300 us */ 30 31 /* APU MBOX */ 32 #define MBOX_WKUP_CFG (0x80) 33 #define MBOX_WKUP_MASK (0x84) 34 #define MBOX_FUNC_CFG (0xb0) 35 #define MBOX_DOMAIN_CFG (0xe0) 36 37 #define MBOX_CTRL_LOCK BIT(0) 38 #define MBOX_NO_MPU_SHIFT (16) 39 #define MBOX_RC_SHIFT (24) 40 41 #define MBOX_RX_NS_SHIFT (16) 42 #define MBOX_RX_DOMAIN_SHIFT (17) 43 #define MBOX_TX_NS_SHIFT (24) 44 #define MBOX_TX_DOMAIN_SHIFT (25) 45 46 #define APU_REG_AO_GLUE_CONFG (APU_AO_CTRL + 0x20) 47 48 #define ENABLE_INFRA_WA 49 50 enum apu_infra_bit_id { 51 APU_INFRA_SYS_APMCU = 1UL, 52 APU_INFRA_SYS_GZ = 2UL, 53 APU_INFRA_SYS_SCP = 3UL, 54 }; 55 56 #define APU_MBOX(i) (APU_MBOX0 + 0x10000 * i) 57 58 #define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG) 59 #define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG) 60 #define APU_MBOX_WKUP_CFG(i) (APU_MBOX(i) + MBOX_WKUP_CFG) 61 62 enum apu_hw_sem_op { 63 HW_SEM_PUT = 0, 64 HW_SEM_GET = 1, 65 }; 66 67 #define HW_SEM_PUT_BIT_SHIFT (16) 68 69 /* bypass mbox register Dump for secure master */ 70 #define APU_MBOX_DBG_EN (0x190f2380) 71 72 /* apu_mbox register definition for mbox addr change*/ 73 #define APU_MBOX_SEMA0_CTRL (0x090) 74 #define APU_MBOX_SEMA0_RST (0x094) 75 #define APU_MBOX_SEMA0_STA (0x098) 76 #define APU_MBOX_SEMA1_CTRL (0x0A0) 77 #define APU_MBOX_SEMA1_RST (0x0A4) 78 #define APU_MBOX_SEMA1_STA (0x0A8) 79 #define APU_MBOX_DUMMY (0x040) 80 #define APU_MBOX_OFFSET(i) (0x10000 * i) 81 82 /* apu infra workaround */ 83 #define APU_INFRA_DISABLE (APU_INFRA_BASE + 0xC18) 84 #define APU_INFRA_ENABLE (APU_INFRA_BASE + 0xC14) 85 #define APU_INFRA_STATUS (APU_INFRA_BASE + 0xC10) 86 #define APU_INFRA_STATUS_MASK (0x1fffe) 87 #define APU_INFRA_HW_SEM (APUSYS_CE_BASE + 0xE00) 88 #define APU_RPC_STATUS (0x190f0044) 89 90 #define APU_INFRA_BIT_OFF (16) 91 #define APU_RPC_STATUS_BIT BIT(0) 92 93 #endif /* APUSYS_RV_PWR_CTL_H */ 94