1 /* 2 * Copyright (c) 2024, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef APUSYS_RV_PWR_CTL_H 8 #define APUSYS_RV_PWR_CTL_H 9 10 #include <platform_def.h> 11 12 #define SUPPORT_APU_CLEAR_MBOX_DUMMY (1) 13 14 enum apu_hw_sem_sys_id { 15 APU_HW_SEM_SYS_APU = 0UL, /* mbox0 */ 16 APU_HW_SEM_SYS_GZ = 1UL, /* mbox1 */ 17 APU_HW_SEM_SYS_SCP = 3UL, /* mbox3 */ 18 APU_HW_SEM_SYS_APMCU = 11UL, /* mbox11 */ 19 }; 20 21 int apusys_rv_pwr_ctrl(uint32_t op); 22 int rv_iommu_hw_sem_unlock(void); 23 int rv_iommu_hw_sem_trylock(void); 24 int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout, 25 uint8_t bypass); 26 27 #define HW_SEM_TIMEOUT (300) /* 300 us */ 28 29 /* APU MBOX */ 30 #define MBOX_WKUP_CFG (0x80) 31 #define MBOX_WKUP_MASK (0x84) 32 #define MBOX_FUNC_CFG (0xb0) 33 #define MBOX_DOMAIN_CFG (0xe0) 34 35 #define MBOX_CTRL_LOCK BIT(0) 36 #define MBOX_NO_MPU_SHIFT (16) 37 #define MBOX_RC_SHIFT (24) 38 39 #define MBOX_RX_NS_SHIFT (16) 40 #define MBOX_RX_DOMAIN_SHIFT (17) 41 #define MBOX_TX_NS_SHIFT (24) 42 #define MBOX_TX_DOMAIN_SHIFT (25) 43 44 #define APU_REG_AO_GLUE_CONFG (APU_AO_CTRL + 0x20) 45 46 #define ENABLE_INFRA_WA 47 48 enum apu_infra_bit_id { 49 APU_INFRA_SYS_APMCU = 1UL, 50 APU_INFRA_SYS_GZ = 2UL, 51 APU_INFRA_SYS_SCP = 3UL, 52 }; 53 54 #define APU_MBOX(i) (APU_MBOX0 + 0x10000 * i) 55 56 #define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG) 57 #define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG) 58 #define APU_MBOX_WKUP_CFG(i) (APU_MBOX(i) + MBOX_WKUP_CFG) 59 60 61 /* bypass mbox register Dump for secure master */ 62 #define APU_MBOX_DBG_EN (0x190f2380) 63 64 /* apu_mbox register definition for mbox addr change*/ 65 #define APU_MBOX_SEMA0_CTRL (0x090) 66 #define APU_MBOX_SEMA0_RST (0x094) 67 #define APU_MBOX_SEMA0_STA (0x098) 68 #define APU_MBOX_SEMA1_CTRL (0x0A0) 69 #define APU_MBOX_SEMA1_RST (0x0A4) 70 #define APU_MBOX_SEMA1_STA (0x0A8) 71 #define APU_MBOX_DUMMY (0x040) 72 #define APU_MBOX_OFFSET(i) (0x10000 * i) 73 74 /* apu infra workaround */ 75 #define APU_INFRA_DISABLE (APU_INFRA_BASE + 0xC18) 76 #define APU_INFRA_ENABLE (APU_INFRA_BASE + 0xC14) 77 #define APU_INFRA_STATUS (APU_INFRA_BASE + 0xC10) 78 #define APU_INFRA_HW_SEM (APUSYS_CE_BASE + 0xE00) 79 #define APU_RPC_STATUS (0x190f0044) 80 81 #endif /* APUSYS_RV_PWR_CTL_H */ 82