1 /* 2 * Copyright (c) 2024, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef APUSYS_RV_MBOX_MPU_H 8 #define APUSYS_RV_MBOX_MPU_H 9 10 #define MPU_EN (0) 11 #define MPU_DIS (1) 12 #define MBOX0_TX_DOMAIN (0) 13 #define MBOX0_TX_NS (1) 14 #define MBOX1_TX_DOMAIN (11) 15 #define MBOX1_TX_NS (1) 16 #define MBOX3_TX_DOMAIN (3) 17 #define MBOX3_TX_NS (0) 18 #define MBOX4_RX_DOMAIN (0) 19 #define MBOX4_RX_NS (0) 20 #define MBOX5_TX_DOMAIN (8) 21 #define MBOX5_TX_NS (0) 22 #define MBOX6_TX_DOMAIN (4) 23 #define MBOX6_TX_NS (1) 24 #define MBOX7_RX_DOMAIN (0) 25 #define MBOX7_RX_NS (0) 26 #define MBOXN_RX_DOMAIN (5) 27 #define MBOXN_RX_NS (0) 28 #define MBOXN_TX_DOMAIN (0) 29 #define MBOXN_TX_NS (0) 30 31 struct mbox_mpu_setting { 32 uint32_t no_mpu; 33 uint32_t rx_ns; 34 uint32_t rx_domain; 35 uint32_t tx_ns; 36 uint32_t tx_domain; 37 }; 38 39 static const struct mbox_mpu_setting mbox_mpu_setting_tab[] = { 40 /* no_mpu, rx_ns, rx_domain, tx_ns, tx_domain */ 41 {MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX0_TX_NS, MBOX0_TX_DOMAIN}, 42 {MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX1_TX_NS, MBOX1_TX_DOMAIN}, 43 {MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN}, 44 {MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX3_TX_NS, MBOX3_TX_DOMAIN}, 45 {MPU_DIS, MBOX4_RX_NS, MBOX4_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN}, 46 {MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX5_TX_NS, MBOX5_TX_DOMAIN}, 47 {MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX6_TX_NS, MBOX6_TX_DOMAIN}, 48 {MPU_DIS, MBOX7_RX_NS, MBOX7_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN}, 49 {MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN}, 50 {MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN}, 51 }; 52 53 #define APU_MBOX_NUM ARRAY_SIZE(mbox_mpu_setting_tab) 54 55 #endif /* APUSYS_RV_MBOX_MPU_H */ 56