1 /* 2 * Copyright (c) 2024, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef APUSYS_DEVAPC_DEF_H 8 #define APUSYS_DEVAPC_DEF_H 9 10 #include <lib/mmio.h> 11 12 #include <devapc/apusys_dapc_v1.h> 13 14 /* Control */ 15 #define SLAVE_RCX_BULK0 SLAVE_FORBID_EXCEPT_D0_D11_NO_PROTECT_D3_D5_D8_SEC_RW 16 #define SLAVE_RCX_BULK1 SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_D8_SEC_RW 17 #define SLAVE_MD32_APB SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW 18 #define SLAVE_ACP_TCU_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 19 #define SLAVE_VCORE SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D3_D5_SEC_RW 20 #define SLAVE_WDEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 21 #define SLAVE_SMMU_IP_REG SLAVE_FORBID_EXCEPT_D3_D5_SEC_RW_D0_D4_D11_NO_PROTECT 22 #define SLAVE_SMMU_NSEC SLAVE_FORBID_EXCEPT_D5_SEC_RW_D0_NO_PROTECT 23 #define SLAVE_SMMU_SEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 24 #define SLAVE_RPC SLAVE_FORBID_EXCEPT_D3_D5_SEC_RW_D0_D11_NO_PROTECT 25 #define SLAVE_PCU SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW 26 #define SLAVE_AO_CTRL SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW 27 #define SLAVE_ACC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW 28 #define SLAVE_PLL SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_D8_SEC_RW 29 #define SLAVE_SEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 30 #define SLAVE_ARE0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 31 #define SLAVE_ARE1 SLAVE_FORBID_EXCEPT_D0_D11_NO_PROTECT_D3_D5_D8_SEC_RW 32 #define SLAVE_RPC_MDLA SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW 33 #define SLAVE_MDLA_DBG SLAVE_FORBID_EXCEPT_D5_SEC_RW 34 #define SLAVE_TOP_PMU SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW 35 #define SLAVE_UNDEFINE0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 36 #define SLAVE_UNDEFINE1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 37 #define SLAVE_UNDEFINE2 SLAVE_FORBID_EXCEPT_D5_SEC_RW 38 #define SLAVE_UNDEFINE3 SLAVE_FORBID_EXCEPT_D5_SEC_RW 39 #define SLAVE_UNDEFINE4 SLAVE_FORBID_EXCEPT_D5_SEC_RW 40 #define SLAVE_UNDEFINE5 SLAVE_FORBID_EXCEPT_D5_SEC_RW 41 #define SLAVE_UNDEFINE6 SLAVE_FORBID_EXCEPT_D5_SEC_RW 42 #define SLAVE_UNDEFINE7 SLAVE_FORBID_EXCEPT_D5_SEC_RW 43 #define SLAVE_UNDEFINE8 SLAVE_FORBID_EXCEPT_D5_SEC_RW 44 #define SLAVE_UNDEFINE9 SLAVE_FORBID_EXCEPT_D5_SEC_RW 45 #define SLAVE_UNDEFINE10 SLAVE_FORBID_EXCEPT_D5_SEC_RW 46 #define SLAVE_DATA_BULK SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 47 #define SLAVE_AO_BCRM SLAVE_FORBID_EXCEPT_D5_SEC_RW 48 #define SLAVE_AO_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_SEC_RW 49 #define SLAVE_AO_DAPC_CON SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 50 #define SLAVE_ACX0_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 51 #define SLAVE_ACX0_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 52 #define SLAVE_ACX0_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 53 #define SLAVE_ACX0_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW 54 #define SLAVE_ACX1_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 55 #define SLAVE_ACX1_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 56 #define SLAVE_ACX1_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 57 #define SLAVE_ACX1_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW 58 #define SLAVE_NCX_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 59 #define SLAVE_NCX_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 60 #define SLAVE_NCX_RPC SLAVE_FORBID_EXCEPT_D5_SEC_RW 61 #define SLAVE_NCX_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW 62 #define SLAVE_MD32_SYSCTRL SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW 63 #define SLAVE_MD32_PMU SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW 64 #define SLAVE_LOG_TOP0 SLAVE_FORBID_EXCEPT_D0_D5_D7_D14_NO_PROTECT 65 #define SLAVE_LOG_TOP1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 66 #define SLAVE_RCX_CFG SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D3_D5_SEC_RW 67 #define SLAVE_ACX_IPS SLAVE_FORBID_EXCEPT_D5_SEC_RW 68 #define SLAVE_RCX_TCU0 SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 69 #define SLAVE_RCX_TCU1 SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 70 #define SLAVE_RCX_TCU2 SLAVE_FORBID_EXCEPT_D5_SEC_RW 71 #define SLAVE_RCX_TCU3 SLAVE_FORBID_EXCEPT_D5_SEC_RW 72 #define SLAVE_RCX_TCU4 SLAVE_FORBID_EXCEPT_D5_SEC_RW 73 #define SLAVE_RCX_TCU5 SLAVE_FORBID_EXCEPT_D5_SEC_RW 74 #define SLAVE_RCX_TCU6 SLAVE_FORBID_EXCEPT_D5_SEC_RW 75 #define SLAVE_RCX_NOC_CFG SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 76 #define SLAVE_MDLA_CORE_CTRL SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 77 #define SLAVE_MDLA_BIU SLAVE_FORBID_EXCEPT_D5_SEC_RW 78 #define SLAVE_MDLA_PMU SLAVE_FORBID_EXCEPT_D5_SEC_RW 79 #define SLAVE_MDLA_CMDE SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 80 #define SLAVE_EDPA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 81 #define SLAVE_EDPA1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 82 #define SLAVE_RCX_CMU SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 83 #define SLAVE_RCX_ACS SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 84 #define SLAVE_MD32_WDT SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW 85 #define SLAVE_MD32_CACHE SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 86 #define SLAVE_MD32_DBG SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_SEC_RW 87 #define SLAVE_INFRA_DBG SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 88 #define SLAVE_IOMMU0_BANK0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 89 #define SLAVE_IOMMU0_BANK1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 90 #define SLAVE_IOMMU0_BANK2 SLAVE_FORBID_EXCEPT_D5_SEC_RW 91 #define SLAVE_IOMMU0_BANK3 SLAVE_FORBID_EXCEPT_D5_SEC_RW 92 #define SLAVE_IOMMU0_BANK4 SLAVE_FORBID_EXCEPT_D5_SEC_RW 93 #define SLAVE_IOMMU1_BANK0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 94 #define SLAVE_IOMMU1_BANK1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 95 #define SLAVE_IOMMU1_BANK2 SLAVE_FORBID_EXCEPT_D5_SEC_RW 96 #define SLAVE_IOMMU1_BANK3 SLAVE_FORBID_EXCEPT_D5_SEC_RW 97 #define SLAVE_IOMMU1_BANK4 SLAVE_FORBID_EXCEPT_D5_SEC_RW 98 #define SLAVE_S0_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 99 #define SLAVE_N0_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 100 #define SLAVE_ACP_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 101 #define SLAVE_S1_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 102 #define SLAVE_N1_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 103 #define SLAVE_SEMA_STIMER SLAVE_FORBID_EXCEPT_D5_SEC_RW 104 #define SLAVE_EMI_CFG SLAVE_FORBID_EXCEPT_D5_SEC_RW 105 #define SLAVE_CPE_SENSOR SLAVE_FORBID_EXCEPT_D5_SEC_RW 106 #define SLAVE_CPE_COEF SLAVE_FORBID_EXCEPT_D5_SEC_RW 107 #define SLAVE_CPE_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW 108 #define SLAVE_TPPA SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW 109 #define SLAVE_SENSOR_ACX0_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 110 #define SLAVE_SENSOR_ACX0_VPU SLAVE_FORBID_EXCEPT_D5_SEC_RW 111 #define SLAVE_SENSOR_ACX1_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 112 #define SLAVE_SENSOR_ACX1_VPU SLAVE_FORBID_EXCEPT_D5_SEC_RW 113 #define SLAVE_SENSOR_NCX_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 114 #define SLAVE_SENSOR_NCX_NVE SLAVE_FORBID_EXCEPT_D5_SEC_RW 115 #define SLAVE_RCX_BCRM SLAVE_FORBID_EXCEPT_D5_SEC_RW 116 #define SLAVE_RCX_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_SEC_RW 117 #define SLAVE_RCX_DAPC_CON SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 118 #define SLAVE_HSE SLAVE_FORBID_EXCEPT_D5_SEC_RW 119 #define SLAVE_RCX_CBFC SLAVE_FORBID_EXCEPT_D5_SEC_RW 120 #define SLAVE_SONC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 121 #define SLAVE_SCMDQ SLAVE_FORBID_EXCEPT_D5_SEC_RW 122 123 #if DEBUG 124 #define SLAVE_PTP_THM SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_SEC_RW 125 #else 126 #define SLAVE_PTP_THM SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 127 #endif 128 129 /* Power Domain: AO */ 130 #define APUSYS_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM (16) 131 #define APUSYS_CTRL_DAPC_AO_DOM_NUM (16) 132 #define APUSYS_CTRL_DAPC_AO_SLAVE_NUM (67) /* 0~66 */ 133 #define DEVAPC_MASK (0x3U) 134 #define DEVAPC_DOM_SHIFT (2) 135 136 /* Power Domain: RCX */ 137 #define APUSYS_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16) 138 #define APUSYS_CTRL_DAPC_RCX_DOM_NUM (16) 139 #define APUSYS_CTRL_DAPC_RCX_SLAVE_NUM (95) /* 0~94 */ 140 141 /* Dump Config */ 142 #undef DUMP_CFG 143 144 #endif 145