131a0b877SKarl Li /* 231a0b877SKarl Li * Copyright (c) 2024, MediaTek Inc. All rights reserved. 331a0b877SKarl Li * 431a0b877SKarl Li * SPDX-License-Identifier: BSD-3-Clause 531a0b877SKarl Li */ 631a0b877SKarl Li 731a0b877SKarl Li #ifndef APUSYS_DEVAPC_DEF_H 831a0b877SKarl Li #define APUSYS_DEVAPC_DEF_H 931a0b877SKarl Li 1031a0b877SKarl Li #include <lib/mmio.h> 1131a0b877SKarl Li 1231a0b877SKarl Li #include <devapc/apusys_dapc_v1.h> 1331a0b877SKarl Li 1431a0b877SKarl Li /* Control */ 1531a0b877SKarl Li #define SLAVE_RCX_BULK0 SLAVE_FORBID_EXCEPT_D0_D11_NO_PROTECT_D3_D5_D8_SEC_RW 1631a0b877SKarl Li #define SLAVE_RCX_BULK1 SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_D8_SEC_RW 1731a0b877SKarl Li #define SLAVE_MD32_APB SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW 1831a0b877SKarl Li #define SLAVE_ACP_TCU_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 1931a0b877SKarl Li #define SLAVE_VCORE SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D3_D5_SEC_RW 2031a0b877SKarl Li #define SLAVE_WDEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 2131a0b877SKarl Li #define SLAVE_SMMU_IP_REG SLAVE_FORBID_EXCEPT_D3_D5_SEC_RW_D0_D4_D11_NO_PROTECT 2231a0b877SKarl Li #define SLAVE_SMMU_NSEC SLAVE_FORBID_EXCEPT_D5_SEC_RW_D0_NO_PROTECT 2331a0b877SKarl Li #define SLAVE_SMMU_SEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 2431a0b877SKarl Li #define SLAVE_RPC SLAVE_FORBID_EXCEPT_D3_D5_SEC_RW_D0_D11_NO_PROTECT 2531a0b877SKarl Li #define SLAVE_PCU SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW 2631a0b877SKarl Li #define SLAVE_AO_CTRL SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW 2731a0b877SKarl Li #define SLAVE_ACC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW 2831a0b877SKarl Li #define SLAVE_PLL SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_D8_SEC_RW 2931a0b877SKarl Li #define SLAVE_SEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 3031a0b877SKarl Li #define SLAVE_ARE0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 3131a0b877SKarl Li #define SLAVE_ARE1 SLAVE_FORBID_EXCEPT_D0_D11_NO_PROTECT_D3_D5_D8_SEC_RW 3231a0b877SKarl Li #define SLAVE_RPC_MDLA SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW 3331a0b877SKarl Li #define SLAVE_MDLA_DBG SLAVE_FORBID_EXCEPT_D5_SEC_RW 3431a0b877SKarl Li #define SLAVE_TOP_PMU SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW 3531a0b877SKarl Li #define SLAVE_UNDEFINE0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 3631a0b877SKarl Li #define SLAVE_UNDEFINE1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 3731a0b877SKarl Li #define SLAVE_UNDEFINE2 SLAVE_FORBID_EXCEPT_D5_SEC_RW 3831a0b877SKarl Li #define SLAVE_UNDEFINE3 SLAVE_FORBID_EXCEPT_D5_SEC_RW 3931a0b877SKarl Li #define SLAVE_UNDEFINE4 SLAVE_FORBID_EXCEPT_D5_SEC_RW 4031a0b877SKarl Li #define SLAVE_UNDEFINE5 SLAVE_FORBID_EXCEPT_D5_SEC_RW 4131a0b877SKarl Li #define SLAVE_UNDEFINE6 SLAVE_FORBID_EXCEPT_D5_SEC_RW 4231a0b877SKarl Li #define SLAVE_UNDEFINE7 SLAVE_FORBID_EXCEPT_D5_SEC_RW 4331a0b877SKarl Li #define SLAVE_UNDEFINE8 SLAVE_FORBID_EXCEPT_D5_SEC_RW 4431a0b877SKarl Li #define SLAVE_UNDEFINE9 SLAVE_FORBID_EXCEPT_D5_SEC_RW 4531a0b877SKarl Li #define SLAVE_UNDEFINE10 SLAVE_FORBID_EXCEPT_D5_SEC_RW 4631a0b877SKarl Li #define SLAVE_DATA_BULK SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 4731a0b877SKarl Li #define SLAVE_AO_BCRM SLAVE_FORBID_EXCEPT_D5_SEC_RW 4831a0b877SKarl Li #define SLAVE_AO_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_SEC_RW 4931a0b877SKarl Li #define SLAVE_AO_DAPC_CON SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 5031a0b877SKarl Li #define SLAVE_ACX0_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 5131a0b877SKarl Li #define SLAVE_ACX0_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 5231a0b877SKarl Li #define SLAVE_ACX0_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 5331a0b877SKarl Li #define SLAVE_ACX0_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW 5431a0b877SKarl Li #define SLAVE_ACX1_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 5531a0b877SKarl Li #define SLAVE_ACX1_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 5631a0b877SKarl Li #define SLAVE_ACX1_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 5731a0b877SKarl Li #define SLAVE_ACX1_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW 5831a0b877SKarl Li #define SLAVE_NCX_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 5931a0b877SKarl Li #define SLAVE_NCX_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 6031a0b877SKarl Li #define SLAVE_NCX_RPC SLAVE_FORBID_EXCEPT_D5_SEC_RW 6131a0b877SKarl Li #define SLAVE_NCX_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW 6231a0b877SKarl Li #define SLAVE_MD32_SYSCTRL SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW 6331a0b877SKarl Li #define SLAVE_MD32_PMU SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW 6431a0b877SKarl Li #define SLAVE_LOG_TOP0 SLAVE_FORBID_EXCEPT_D0_D5_D7_D14_NO_PROTECT 6531a0b877SKarl Li #define SLAVE_LOG_TOP1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 6631a0b877SKarl Li #define SLAVE_RCX_CFG SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D3_D5_SEC_RW 6731a0b877SKarl Li #define SLAVE_ACX_IPS SLAVE_FORBID_EXCEPT_D5_SEC_RW 6831a0b877SKarl Li #define SLAVE_RCX_TCU0 SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 6931a0b877SKarl Li #define SLAVE_RCX_TCU1 SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 7031a0b877SKarl Li #define SLAVE_RCX_TCU2 SLAVE_FORBID_EXCEPT_D5_SEC_RW 7131a0b877SKarl Li #define SLAVE_RCX_TCU3 SLAVE_FORBID_EXCEPT_D5_SEC_RW 7231a0b877SKarl Li #define SLAVE_RCX_TCU4 SLAVE_FORBID_EXCEPT_D5_SEC_RW 7331a0b877SKarl Li #define SLAVE_RCX_TCU5 SLAVE_FORBID_EXCEPT_D5_SEC_RW 7431a0b877SKarl Li #define SLAVE_RCX_TCU6 SLAVE_FORBID_EXCEPT_D5_SEC_RW 7531a0b877SKarl Li #define SLAVE_RCX_NOC_CFG SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 7631a0b877SKarl Li #define SLAVE_MDLA_CORE_CTRL SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 7731a0b877SKarl Li #define SLAVE_MDLA_BIU SLAVE_FORBID_EXCEPT_D5_SEC_RW 7831a0b877SKarl Li #define SLAVE_MDLA_PMU SLAVE_FORBID_EXCEPT_D5_SEC_RW 7931a0b877SKarl Li #define SLAVE_MDLA_CMDE SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 8031a0b877SKarl Li #define SLAVE_EDPA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 8131a0b877SKarl Li #define SLAVE_EDPA1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 8231a0b877SKarl Li #define SLAVE_RCX_CMU SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 8331a0b877SKarl Li #define SLAVE_RCX_ACS SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 8431a0b877SKarl Li #define SLAVE_MD32_WDT SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW 8531a0b877SKarl Li #define SLAVE_MD32_CACHE SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 8631a0b877SKarl Li #define SLAVE_MD32_DBG SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_SEC_RW 8731a0b877SKarl Li #define SLAVE_INFRA_DBG SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 8831a0b877SKarl Li #define SLAVE_IOMMU0_BANK0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 8931a0b877SKarl Li #define SLAVE_IOMMU0_BANK1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9031a0b877SKarl Li #define SLAVE_IOMMU0_BANK2 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9131a0b877SKarl Li #define SLAVE_IOMMU0_BANK3 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9231a0b877SKarl Li #define SLAVE_IOMMU0_BANK4 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9331a0b877SKarl Li #define SLAVE_IOMMU1_BANK0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9431a0b877SKarl Li #define SLAVE_IOMMU1_BANK1 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9531a0b877SKarl Li #define SLAVE_IOMMU1_BANK2 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9631a0b877SKarl Li #define SLAVE_IOMMU1_BANK3 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9731a0b877SKarl Li #define SLAVE_IOMMU1_BANK4 SLAVE_FORBID_EXCEPT_D5_SEC_RW 9831a0b877SKarl Li #define SLAVE_S0_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 9931a0b877SKarl Li #define SLAVE_N0_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 10031a0b877SKarl Li #define SLAVE_ACP_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 10131a0b877SKarl Li #define SLAVE_S1_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 10231a0b877SKarl Li #define SLAVE_N1_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW 10331a0b877SKarl Li #define SLAVE_SEMA_STIMER SLAVE_FORBID_EXCEPT_D5_SEC_RW 10431a0b877SKarl Li #define SLAVE_EMI_CFG SLAVE_FORBID_EXCEPT_D5_SEC_RW 10531a0b877SKarl Li #define SLAVE_CPE_SENSOR SLAVE_FORBID_EXCEPT_D5_SEC_RW 10631a0b877SKarl Li #define SLAVE_CPE_COEF SLAVE_FORBID_EXCEPT_D5_SEC_RW 10731a0b877SKarl Li #define SLAVE_CPE_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW 10831a0b877SKarl Li #define SLAVE_TPPA SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW 10931a0b877SKarl Li #define SLAVE_SENSOR_ACX0_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 11031a0b877SKarl Li #define SLAVE_SENSOR_ACX0_VPU SLAVE_FORBID_EXCEPT_D5_SEC_RW 11131a0b877SKarl Li #define SLAVE_SENSOR_ACX1_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 11231a0b877SKarl Li #define SLAVE_SENSOR_ACX1_VPU SLAVE_FORBID_EXCEPT_D5_SEC_RW 11331a0b877SKarl Li #define SLAVE_SENSOR_NCX_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW 11431a0b877SKarl Li #define SLAVE_SENSOR_NCX_NVE SLAVE_FORBID_EXCEPT_D5_SEC_RW 11531a0b877SKarl Li #define SLAVE_RCX_BCRM SLAVE_FORBID_EXCEPT_D5_SEC_RW 11631a0b877SKarl Li #define SLAVE_RCX_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_SEC_RW 11731a0b877SKarl Li #define SLAVE_RCX_DAPC_CON SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 11831a0b877SKarl Li #define SLAVE_HSE SLAVE_FORBID_EXCEPT_D5_SEC_RW 11931a0b877SKarl Li #define SLAVE_RCX_CBFC SLAVE_FORBID_EXCEPT_D5_SEC_RW 12031a0b877SKarl Li #define SLAVE_SONC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW 12131a0b877SKarl Li #define SLAVE_SCMDQ SLAVE_FORBID_EXCEPT_D5_SEC_RW 12231a0b877SKarl Li 12331a0b877SKarl Li #if DEBUG 12431a0b877SKarl Li #define SLAVE_PTP_THM SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_SEC_RW 12531a0b877SKarl Li #else 12631a0b877SKarl Li #define SLAVE_PTP_THM SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW 12731a0b877SKarl Li #endif 12831a0b877SKarl Li 12931a0b877SKarl Li /* Power Domain: AO */ 13031a0b877SKarl Li #define APUSYS_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM (16) 13131a0b877SKarl Li #define APUSYS_CTRL_DAPC_AO_DOM_NUM (16) 13231a0b877SKarl Li #define APUSYS_CTRL_DAPC_AO_SLAVE_NUM (67) /* 0~66 */ 13331a0b877SKarl Li #define DEVAPC_MASK (0x3U) 13431a0b877SKarl Li #define DEVAPC_DOM_SHIFT (2) 13531a0b877SKarl Li 13631a0b877SKarl Li /* Power Domain: RCX */ 13731a0b877SKarl Li #define APUSYS_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16) 13831a0b877SKarl Li #define APUSYS_CTRL_DAPC_RCX_DOM_NUM (16) 13931a0b877SKarl Li #define APUSYS_CTRL_DAPC_RCX_SLAVE_NUM (95) /* 0~94 */ 14031a0b877SKarl Li 14131a0b877SKarl Li /* Dump Config */ 142*31137e1bSGavin Liu #undef DUMP_CFG 14331a0b877SKarl Li 14431a0b877SKarl Li #endif 145