1b5900c92SKarl Li /* 2*7ed4d67cSKarl Li * Copyright (c) 2023-2024, MediaTek Inc. All rights reserved. 3b5900c92SKarl Li * 4b5900c92SKarl Li * SPDX-License-Identifier: BSD-3-Clause 5b5900c92SKarl Li */ 6b5900c92SKarl Li 7b5900c92SKarl Li #ifndef APUSYS_SECURITY_CTRL_PLAT_H 8b5900c92SKarl Li #define APUSYS_SECURITY_CTRL_PLAT_H 9b5900c92SKarl Li 10b5900c92SKarl Li #include <platform_def.h> 11b5900c92SKarl Li 12b5900c92SKarl Li #define SOC2APU_SET1_0 (APU_SEC_CON + 0x0c) 13b5900c92SKarl Li #define SOC2APU_SET1_1 (APU_SEC_CON + 0x10) 14b5900c92SKarl Li 15b5900c92SKarl Li #define REG_DOMAIN_NUM (8) 16b5900c92SKarl Li #define REG_DOMAIN_BITS (4) 17b5900c92SKarl Li #define DOMAIN_REMAP_SEL BIT(6) 18b5900c92SKarl Li 19b5900c92SKarl Li #define D0_REMAP_DOMAIN (0) 20b5900c92SKarl Li #define D1_REMAP_DOMAIN (1) 21b5900c92SKarl Li #define D2_REMAP_DOMAIN (2) 22b5900c92SKarl Li #define D3_REMAP_DOMAIN (3) 23b5900c92SKarl Li #define D4_REMAP_DOMAIN (4) 24b5900c92SKarl Li #define D5_REMAP_DOMAIN (14) 25b5900c92SKarl Li #define D6_REMAP_DOMAIN (6) 26b5900c92SKarl Li #define D7_REMAP_DOMAIN (14) 27b5900c92SKarl Li #define D8_REMAP_DOMAIN (8) 28b5900c92SKarl Li #define D9_REMAP_DOMAIN (9) 29b5900c92SKarl Li #define D10_REMAP_DOMAIN (10) 30b5900c92SKarl Li #define D11_REMAP_DOMAIN (11) 31b5900c92SKarl Li #define D12_REMAP_DOMAIN (12) 32b5900c92SKarl Li #define D13_REMAP_DOMAIN (13) 33b5900c92SKarl Li #define D14_REMAP_DOMAIN (14) 34b5900c92SKarl Li #define D15_REMAP_DOMAIN (15) 35b5900c92SKarl Li 36b5900c92SKarl Li void apusys_security_ctrl_init(void); 37*7ed4d67cSKarl Li int apusys_plat_setup_sec_mem(void); 38b5900c92SKarl Li 39b5900c92SKarl Li #endif /* APUSYS_SECURITY_CTRL_PLAT_H */ 40