1*83f836c9SKarl Li /* 2*83f836c9SKarl Li * Copyright (c) 2023-2024, MediaTek Inc. All rights reserved. 3*83f836c9SKarl Li * 4*83f836c9SKarl Li * SPDX-License-Identifier: BSD-3-Clause 5*83f836c9SKarl Li */ 6*83f836c9SKarl Li 7*83f836c9SKarl Li #ifndef APUSYS_RV_MBOX_MPU_H 8*83f836c9SKarl Li #define APUSYS_RV_MBOX_MPU_H 9*83f836c9SKarl Li 10*83f836c9SKarl Li #define MPU_EN (0) 11*83f836c9SKarl Li #define MPU_DIS (1) 12*83f836c9SKarl Li #define MBOX0_TX_DOMAIN (0) 13*83f836c9SKarl Li #define MBOX0_TX_NS (1) 14*83f836c9SKarl Li #define MBOX4_RX_DOMAIN (0) 15*83f836c9SKarl Li #define MBOX4_RX_NS (0) 16*83f836c9SKarl Li #define MBOX5_TX_DOMAIN (3) 17*83f836c9SKarl Li #define MBOX5_TX_NS (0) 18*83f836c9SKarl Li #define MBOXN_RX_DOMAIN (5) 19*83f836c9SKarl Li #define MBOXN_RX_NS (1) 20*83f836c9SKarl Li #define MBOXN_TX_DOMAIN (0) 21*83f836c9SKarl Li #define MBOXN_TX_NS (0) 22*83f836c9SKarl Li 23*83f836c9SKarl Li struct mbox_mpu_setting { 24*83f836c9SKarl Li uint32_t no_mpu; 25*83f836c9SKarl Li uint32_t rx_ns; 26*83f836c9SKarl Li uint32_t rx_domain; 27*83f836c9SKarl Li uint32_t tx_ns; 28*83f836c9SKarl Li uint32_t tx_domain; 29*83f836c9SKarl Li }; 30*83f836c9SKarl Li 31*83f836c9SKarl Li static const struct mbox_mpu_setting mbox_mpu_setting_tab[] = { 32*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX0_TX_NS, MBOX0_TX_DOMAIN }, 33*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, 34*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, 35*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, 36*83f836c9SKarl Li { MPU_DIS, MBOX4_RX_NS, MBOX4_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, 37*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX5_TX_NS, MBOX5_TX_DOMAIN }, 38*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, 39*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, 40*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, 41*83f836c9SKarl Li { MPU_EN, MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN }, 42*83f836c9SKarl Li }; 43*83f836c9SKarl Li 44*83f836c9SKarl Li #define APU_MBOX_NUM ARRAY_SIZE(mbox_mpu_setting_tab) 45*83f836c9SKarl Li 46*83f836c9SKarl Li #endif /* APUSYS_RV_MBOX_MPU_H */ 47