1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef APUSYS_POWER_H 8 #define APUSYS_POWER_H 9 10 #include <platform_def.h> 11 12 enum APU_CLKSRC_ID { 13 PLL_CONN = 0, /* MNOC */ 14 PLL_UP, 15 PLL_VPU, 16 PLL_DLA, 17 PLL_NUM, 18 }; 19 20 enum APU_ARE_ID { 21 APU_ARE0 = 0, 22 APU_ARE1, 23 APU_ARE2, 24 APU_ARE_NUM, 25 }; 26 27 enum APU_D4_SLV_CTRL { 28 D4_SLV_OFF = 0, 29 D4_SLV_ON, 30 }; 31 32 #define APU_POLL_STEP_US (5) 33 34 #define OUT_CLK_FREQ_MIN (1500) 35 #define BASIC_CLK_FREQ (26) 36 #define DDS_SHIFT (14) 37 38 #define APUPLL0_DEFAULT_FREQ (900) 39 #define APUPLL1_DEFAULT_FREQ (832) 40 #define APUPLL2_DEFAULT_FREQ (700) 41 #define APUPLL3_DEFAULT_FREQ (700) 42 43 #define APU_TOP_ON_POLLING_TIMEOUT_US (10000) 44 #define APU_TOP_OFF_POLLING_TIMEOUT_US (5 * APU_TOP_ON_POLLING_TIMEOUT_US) 45 #define APU_ARE_POLLING_TIMEOUT_US (10000) 46 47 /* APU related reg */ 48 #define APU_VCORE_BASE (APU_RCX_VCORE_CONFIG) 49 #define APU_RCX_BASE (APU_RCX_CONFIG) 50 #define APU_RPC_BASE (APU_RPCTOP) 51 #define APU_PCU_BASE (APU_PCUTOP) 52 #define APU_ARE0_BASE (APU_ARETOP_ARE0) 53 #define APU_ARE1_BASE (APU_ARETOP_ARE1) 54 #define APU_ARE2_BASE (APU_ARETOP_ARE2) 55 #define APU_MBOX0_BASE (APU_MBOX0) 56 #define APU_AO_CTL_BASE (APU_AO_CTRL) 57 #define APU_PLL_BASE (APU_PLL) 58 #define APU_ACC_BASE (APU_ACC) 59 #define APU_ACX0_RPC_LITE_BASE (APU_ACX0_RPC_LITE) 60 61 /* RPC offset define */ 62 #define APU_RPC_TOP_CON (0x0000) 63 #define APU_RPC_TOP_SEL (0x0004) 64 #define APU_RPC_STATUS (0x0014) 65 #define APU_RPC_TOP_SEL_1 (0x0018) 66 #define APU_RPC_HW_CON (0x001c) 67 #define APU_RPC_INTF_PWR_RDY (0x0044) 68 #define APU_RPC_SW_TYPE0 (0x0200) 69 70 /* RPC control */ 71 #define SRAM_AOC_ISO_CLR BIT(7) 72 #define BUCK_ELS_EN_SET BIT(10) 73 #define BUCK_ELS_EN_CLR BIT(11) 74 #define BUCK_AO_RST_B_SET BIT(12) 75 #define BUCK_AO_RST_B_CLR BIT(13) 76 #define BUCK_PROT_REQ_SET BIT(14) 77 #define BUCK_PROT_REQ_CLR BIT(15) 78 #define SW_TYPE BIT(1) 79 #define RPC_CTRL (0x0000009e) 80 #define RPC_TOP_CTRL (0x0800501e) 81 #define RPC_TOP_CTRL1 BIT(20) 82 #define AFC_ENA BIT(16) 83 #define REG_WAKEUP_SET BIT(8) 84 #define REG_WAKEUP_CLR BIT(12) 85 #define PWR_RDY BIT(0) 86 #define PWR_OFF (0) 87 #define RPC_STATUS_RDY BIT(29) 88 #define RSV10 BIT(10) 89 #define CLR_IRQ (0x6) 90 #define SLEEP_REQ BIT(0) 91 92 /* PLL offset define */ 93 #define PLL4H_PLL1_CON1 (0x000c) 94 #define PLL4H_PLL2_CON1 (0x001c) 95 #define PLL4H_PLL3_CON1 (0x002c) 96 #define PLL4H_PLL4_CON1 (0x003c) 97 #define PLL4HPLL_FHCTL_HP_EN (0x0e00) 98 #define PLL4HPLL_FHCTL_CLK_CON (0x0e08) 99 #define PLL4HPLL_FHCTL_RST_CON (0x0e0c) 100 #define PLL4HPLL_FHCTL0_CFG (0x0e3c) 101 #define PLL4HPLL_FHCTL0_DDS (0x0e44) 102 #define PLL4HPLL_FHCTL1_CFG (0x0e50) 103 #define PLL4HPLL_FHCTL1_DDS (0x0e58) 104 #define PLL4HPLL_FHCTL2_CFG (0x0e64) 105 #define PLL4HPLL_FHCTL2_DDS (0x0e6c) 106 #define PLL4HPLL_FHCTL3_CFG (0x0e78) 107 #define PLL4HPLL_FHCTL3_DDS (0x0e80) 108 109 /* PLL control */ 110 #define PLL4H_PLL_HP_EN (0xf) 111 #define PLL4H_PLL_HP_CLKEN (0xf) 112 #define PLL4H_PLL_HP_SWRSTB (0xf) 113 #define FHCTL0_EN BIT(0) 114 #define SFSTR0_EN BIT(2) 115 #define RG_PLL_POSDIV_MASK (0x7) 116 #define RG_PLL_POSDIV_SFT (24) 117 #define FHCTL_PLL_TGL_ORG BIT(31) 118 119 /* ACC offset define */ 120 #define APU_ACC_CONFG_SET0 (0x0000) 121 #define APU_ACC_CONFG_SET1 (0x0004) 122 #define APU_ACC_CONFG_SET2 (0x0008) 123 #define APU_ACC_CONFG_SET3 (0x000c) 124 #define APU_ACC_CONFG_CLR0 (0x0040) 125 #define APU_ACC_CONFG_CLR1 (0x0044) 126 #define APU_ACC_CONFG_CLR2 (0x0048) 127 #define APU_ACC_CONFG_CLR3 (0x004c) 128 #define APU_ACC_CLK_INV_EN_SET (0x00e8) 129 #define APU_ACC_AUTO_CTRL_SET2 (0x0128) 130 #define APU_ACC_AUTO_CTRL_SET3 (0x012c) 131 132 /* ACC control */ 133 #define CGEN_SOC BIT(2) 134 #define HW_CTRL_EN BIT(15) 135 #define CLK_REQ_SW_EN BIT(8) 136 #define CLK_INV_EN (0xaaa8) 137 138 /* ARE offset define */ 139 #define APU_ARE_INI_CTRL (0x0000) 140 #define APU_ARE_GLO_FSM (0x0048) 141 #define APU_ARE_ENTRY0_SRAM_H (0x0c00) 142 #define APU_ARE_ENTRY0_SRAM_L (0x0800) 143 #define APU_ARE_ENTRY1_SRAM_H (0x0c04) 144 #define APU_ARE_ENTRY1_SRAM_L (0x0804) 145 #define APU_ARE_ENTRY2_SRAM_H (0x0c08) 146 #define APU_ARE_ENTRY2_SRAM_L (0x0808) 147 148 /* ARE control */ 149 #define ARE_ENTRY_CFG_H (0x00140000) 150 #define ARE0_ENTRY2_CFG_L (0x004e0804) 151 #define ARE1_ENTRY2_CFG_L (0x004e0806) 152 #define ARE2_ENTRY2_CFG_L (0x004e0807) 153 #define ARE_GLO_FSM_IDLE BIT(0) 154 #define ARE_ENTRY0_SRAM_H_INIT (0x12345678) 155 #define ARE_ENTRY0_SRAM_L_INIT (0x89abcdef) 156 #define ARE_ENTRY1_SRAM_H_INIT (0xfedcba98) 157 #define ARE_ENTRY1_SRAM_L_INIT (0x76543210) 158 #define ARE_CONFG_INI BIT(2) 159 160 /* VCORE offset define */ 161 #define APUSYS_VCORE_CG_CLR (0x0008) 162 163 /* RCX offset define */ 164 #define APU_RCX_CG_CLR (0x0008) 165 166 /* SPM offset define */ 167 #define APUSYS_BUCK_ISOLATION (0x03ec) 168 169 /* SPM control*/ 170 #define IPU_EXT_BUCK_ISO (0x21) 171 172 /* apu_rcx_ao_ctrl */ 173 #define CSR_DUMMY_0_ADDR (0x0024) 174 175 /* apu_rcx_ao_ctrl control */ 176 #define VCORE_ARE_REQ BIT(2) 177 178 /* xpu2apusys */ 179 #define INFRA_FMEM_BUS_u_SI21_CTRL_0 (0x002c) 180 #define INFRA_FMEM_BUS_u_SI22_CTRL_0 (0x0044) 181 #define INFRA_FMEM_BUS_u_SI11_CTRL_0 (0x0048) 182 #define INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0 (0x01d0) 183 184 /* xpu2apusys */ 185 #define INFRA_FMEM_BUS_u_SI21_CTRL_EN BIT(12) 186 #define INFRA_FMEM_BUS_u_SI22_CTRL_EN BIT(13) 187 #define INFRA_FMEM_BUS_u_SI11_CTRL_EN BIT(11) 188 #define INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN BIT(15) 189 190 /* PCU offset define */ 191 #define APU_PCU_CTRL_SET (0x0000) 192 #define APU_PCU_BUCK_STEP_SEL (0x0030) 193 #define APU_PCU_BUCK_ON_DAT0_L (0x0080) 194 #define APU_PCU_BUCK_ON_DAT0_H (0x0084) 195 #define APU_PCU_BUCK_ON_DAT1_L (0x0088) 196 #define APU_PCU_BUCK_ON_DAT1_H (0x008c) 197 #define APU_PCU_BUCK_OFF_DAT0_L (0x00a0) 198 #define APU_PCU_BUCK_OFF_DAT0_H (0x00a4) 199 #define APU_PCU_BUCK_OFF_DAT1_L (0x00a8) 200 #define APU_PCU_BUCK_OFF_DAT1_H (0x00ac) 201 #define APU_PCU_BUCK_ON_SLE0 (0x00c0) 202 #define APU_PCU_BUCK_ON_SLE1 (0x00c4) 203 #define APU_PCU_BUCK_ON_SETTLE_TIME (0x012c) 204 205 /* PCU initial data */ 206 #define MT6359P_RG_BUCK_VMODEM_EN_ADDR (0x1688) 207 #define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR (0x1f2e) 208 #define BUCK_VAPU_PMIC_REG_EN_ADDR MT6359P_RG_BUCK_VMODEM_EN_ADDR 209 #define BUCK_VAPU_SRAM_PMIC_REG_EN_ADDR MT6359P_RG_LDO_VSRAM_MD_EN_ADDR 210 211 /* PCU control */ 212 #define AUTO_BUCK_EN BIT(16) 213 #define BUCK_ON_OFF_CMD_EN (0x33) 214 #define BUCK_OFFSET_SFT (16) 215 #define BUCK_ON_CMD (0x1) 216 #define BUCK_OFF_CMD (0x0) 217 #define CMD_OP (0x4) 218 219 /* RPC lite offset define */ 220 #define APU_RPC_SW_TYPE2 (0x0208) 221 #define APU_RPC_SW_TYPE3 (0x020c) 222 #define APU_RPC_SW_TYPE4 (0x0210) 223 #define APU_RPC_SW_TYPE5 (0x0214) 224 #define APU_RPC_SW_TYPE6 (0x0218) 225 #define APU_RPC_SW_TYPE7 (0x021c) 226 #define APU_RPC_SW_TYPE8 (0x0220) 227 #define APU_RPC_SW_TYPE9 (0x0224) 228 229 /* power flow sync */ 230 #define PWR_FLOW_SYNC_REG (0x0440) 231 232 #define CG_CLR (0xffffffff) 233 234 int apusys_power_init(void); 235 int apusys_kernel_apusys_pwr_top_on(void); 236 int apusys_kernel_apusys_pwr_top_off(void); 237 238 #endif /* APUSYS_POWER_H */ 239