1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <inttypes.h> 8 9 /* TF-A system header */ 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 17 /* Vendor header */ 18 #include "apusys.h" 19 #include "apusys_power.h" 20 #include "apusys_rv.h" 21 #include <mtk_mmap_pool.h> 22 23 static spinlock_t apu_lock; 24 static bool apusys_top_on; 25 26 static int apu_poll(uintptr_t reg, uint32_t mask, uint32_t value, uint32_t timeout_us) 27 { 28 uint32_t reg_val, count; 29 30 count = timeout_us / APU_POLL_STEP_US; 31 if (count == 0) { 32 count = 1; 33 } 34 35 do { 36 reg_val = mmio_read_32(reg); 37 if ((reg_val & mask) == value) { 38 return 0; 39 } 40 41 udelay(APU_POLL_STEP_US); 42 } while (--count); 43 44 ERROR(MODULE_TAG "Timeout polling APU register %#" PRIxPTR "\n", reg); 45 ERROR(MODULE_TAG "Read value 0x%x, expected 0x%x\n", reg_val, 46 (value == 0U) ? (reg_val & ~mask) : (reg_val | mask)); 47 48 return -1; 49 } 50 51 static void apu_backup_restore(enum APU_BACKUP_RESTORE_CTRL ctrl) 52 { 53 int i; 54 static struct apu_restore_data apu_restore_data[] = { 55 { UP_NORMAL_DOMAIN_NS, 0 }, 56 { UP_PRI_DOMAIN_NS, 0 }, 57 { UP_IOMMU_CTRL, 0 }, 58 { UP_CORE0_VABASE0, 0 }, 59 { UP_CORE0_MVABASE0, 0 }, 60 { UP_CORE0_VABASE1, 0 }, 61 { UP_CORE0_MVABASE1, 0 }, 62 { UP_CORE0_VABASE2, 0 }, 63 { UP_CORE0_MVABASE2, 0 }, 64 { UP_CORE0_VABASE3, 0 }, 65 { UP_CORE0_MVABASE3, 0 }, 66 { MD32_SYS_CTRL, 0 }, 67 { MD32_CLK_CTRL, 0 }, 68 { UP_WAKE_HOST_MASK0, 0 } 69 }; 70 71 switch (ctrl) { 72 case APU_CTRL_BACKUP: 73 for (i = 0; i < ARRAY_SIZE(apu_restore_data); i++) { 74 apu_restore_data[i].data = mmio_read_32(apu_restore_data[i].reg); 75 } 76 break; 77 case APU_CTRL_RESTORE: 78 for (i = 0; i < ARRAY_SIZE(apu_restore_data); i++) { 79 mmio_write_32(apu_restore_data[i].reg, apu_restore_data[i].data); 80 } 81 break; 82 default: 83 ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, ctrl); 84 break; 85 } 86 } 87 88 static void apu_xpu2apusys_d4_slv_en(enum APU_D4_SLV_CTRL en) 89 { 90 switch (en) { 91 case D4_SLV_OFF: 92 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0, 93 INFRA_FMEM_BUS_u_SI21_CTRL_EN); 94 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0, 95 INFRA_FMEM_BUS_u_SI22_CTRL_EN); 96 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0, 97 INFRA_FMEM_BUS_u_SI11_CTRL_EN); 98 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0, 99 INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN); 100 break; 101 case D4_SLV_ON: 102 mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0, 103 INFRA_FMEM_BUS_u_SI21_CTRL_EN); 104 mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0, 105 INFRA_FMEM_BUS_u_SI22_CTRL_EN); 106 mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0, 107 INFRA_FMEM_BUS_u_SI11_CTRL_EN); 108 mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0, 109 INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN); 110 break; 111 default: 112 ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, en); 113 break; 114 } 115 } 116 117 static void apu_pwr_flow_remote_sync(uint32_t cfg) 118 { 119 mmio_write_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG, (cfg & 0x1)); 120 } 121 122 int apusys_kernel_apusys_pwr_top_on(void) 123 { 124 int ret; 125 126 spin_lock(&apu_lock); 127 128 if (apusys_top_on == true) { 129 INFO(MODULE_TAG "%s: APUSYS already powered on!\n", __func__); 130 spin_unlock(&apu_lock); 131 return 0; 132 } 133 134 apu_pwr_flow_remote_sync(1); 135 136 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, AFC_ENA); 137 138 mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_SET); 139 140 ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY, 141 PWR_RDY, PWR_RDY, APU_TOP_ON_POLLING_TIMEOUT_US); 142 if (ret != 0) { 143 ERROR(MODULE_TAG "%s polling RPC RDY timeout, ret %d\n", __func__, ret); 144 spin_unlock(&apu_lock); 145 return ret; 146 } 147 148 ret = apu_poll(APU_RPC_BASE + APU_RPC_STATUS, 149 RPC_STATUS_RDY, RPC_STATUS_RDY, APU_TOP_ON_POLLING_TIMEOUT_US); 150 if (ret != 0) { 151 ERROR(MODULE_TAG "%s polling ARE FSM timeout, ret %d\n", __func__, ret); 152 spin_unlock(&apu_lock); 153 return ret; 154 } 155 156 mmio_write_32(APU_VCORE_BASE + APUSYS_VCORE_CG_CLR, CG_CLR); 157 mmio_write_32(APU_RCX_BASE + APU_RCX_CG_CLR, CG_CLR); 158 159 apu_xpu2apusys_d4_slv_en(D4_SLV_OFF); 160 161 apu_backup_restore(APU_CTRL_RESTORE); 162 163 apusys_top_on = true; 164 165 spin_unlock(&apu_lock); 166 return ret; 167 } 168 169 static void apu_sleep_rpc_rcx(void) 170 { 171 mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_CLR); 172 udelay(10); 173 174 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, (RPC_CTRL | RSV10)); 175 udelay(10); 176 177 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, CLR_IRQ); 178 udelay(10); 179 180 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, SLEEP_REQ); 181 udelay(100); 182 } 183 184 int apusys_kernel_apusys_pwr_top_off(void) 185 { 186 int ret; 187 188 spin_lock(&apu_lock); 189 190 if (apusys_top_on == false) { 191 INFO(MODULE_TAG "%s: APUSYS already powered off!\n", __func__); 192 spin_unlock(&apu_lock); 193 return 0; 194 } 195 196 apu_backup_restore(APU_CTRL_BACKUP); 197 198 apu_xpu2apusys_d4_slv_en(D4_SLV_ON); 199 200 if (mmio_read_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG) == 0) { 201 apu_pwr_flow_remote_sync(1); 202 } else { 203 apu_sleep_rpc_rcx(); 204 } 205 206 ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY, 207 PWR_RDY, PWR_OFF, APU_TOP_OFF_POLLING_TIMEOUT_US); 208 if (ret != 0) { 209 ERROR(MODULE_TAG "%s timeout to wait RPC sleep (val:%d), ret %d\n", 210 __func__, APU_TOP_OFF_POLLING_TIMEOUT_US, ret); 211 spin_unlock(&apu_lock); 212 return ret; 213 } 214 215 apusys_top_on = false; 216 217 spin_unlock(&apu_lock); 218 return ret; 219 } 220 221 static void get_pll_pcw(const uint32_t clk_rate, uint32_t *r1, uint32_t *r2) 222 { 223 unsigned int fvco = clk_rate; 224 unsigned int pcw_val; 225 unsigned int postdiv_val = 1; 226 unsigned int postdiv_reg = 0; 227 228 while (fvco <= OUT_CLK_FREQ_MIN) { 229 postdiv_val = postdiv_val << 1; 230 postdiv_reg = postdiv_reg + 1; 231 fvco = fvco << 1; 232 } 233 234 pcw_val = (fvco * (1 << DDS_SHIFT)) / BASIC_CLK_FREQ; 235 236 if (postdiv_reg == 0) { 237 pcw_val = pcw_val * 2; 238 postdiv_val = postdiv_val << 1; 239 postdiv_reg = postdiv_reg + 1; 240 } 241 242 *r1 = postdiv_reg; 243 *r2 = pcw_val; 244 } 245 246 static void apu_pll_init(void) 247 { 248 const uint32_t pll_hfctl_cfg[PLL_NUM] = { 249 PLL4HPLL_FHCTL0_CFG, 250 PLL4HPLL_FHCTL1_CFG, 251 PLL4HPLL_FHCTL2_CFG, 252 PLL4HPLL_FHCTL3_CFG 253 }; 254 const uint32_t pll_con1[PLL_NUM] = { 255 PLL4H_PLL1_CON1, 256 PLL4H_PLL2_CON1, 257 PLL4H_PLL3_CON1, 258 PLL4H_PLL4_CON1 259 }; 260 const uint32_t pll_fhctl_dds[PLL_NUM] = { 261 PLL4HPLL_FHCTL0_DDS, 262 PLL4HPLL_FHCTL1_DDS, 263 PLL4HPLL_FHCTL2_DDS, 264 PLL4HPLL_FHCTL3_DDS 265 }; 266 const uint32_t pll_freq_out[PLL_NUM] = { 267 APUPLL0_DEFAULT_FREQ, 268 APUPLL1_DEFAULT_FREQ, 269 APUPLL2_DEFAULT_FREQ, 270 APUPLL3_DEFAULT_FREQ 271 }; 272 uint32_t pcw_val, posdiv_val; 273 int pll_idx; 274 275 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_RST_CON, PLL4H_PLL_HP_SWRSTB); 276 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_HP_EN, PLL4H_PLL_HP_EN); 277 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_CLK_CON, PLL4H_PLL_HP_CLKEN); 278 279 for (pll_idx = 0; pll_idx < PLL_NUM; pll_idx++) { 280 mmio_setbits_32(APU_PLL_BASE + pll_hfctl_cfg[pll_idx], (FHCTL0_EN | SFSTR0_EN)); 281 282 posdiv_val = 0; 283 pcw_val = 0; 284 get_pll_pcw(pll_freq_out[pll_idx], &posdiv_val, &pcw_val); 285 286 mmio_clrsetbits_32(APU_PLL_BASE + pll_con1[pll_idx], 287 (RG_PLL_POSDIV_MASK << RG_PLL_POSDIV_SFT), 288 (posdiv_val << RG_PLL_POSDIV_SFT)); 289 mmio_write_32(APU_PLL_BASE + pll_fhctl_dds[pll_idx], 290 (FHCTL_PLL_TGL_ORG | pcw_val)); 291 } 292 } 293 294 static void apu_acc_init(void) 295 { 296 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR0, CGEN_SOC); 297 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET0, HW_CTRL_EN); 298 299 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR1, CGEN_SOC); 300 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET1, HW_CTRL_EN); 301 302 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR2, CGEN_SOC); 303 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET2, HW_CTRL_EN); 304 mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET2, CLK_REQ_SW_EN); 305 306 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR3, CGEN_SOC); 307 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET3, HW_CTRL_EN); 308 mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET3, CLK_REQ_SW_EN); 309 310 mmio_write_32(APU_ACC_BASE + APU_ACC_CLK_INV_EN_SET, CLK_INV_EN); 311 } 312 313 static void apu_buck_off_cfg(void) 314 { 315 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_SET); 316 udelay(10); 317 318 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_SET); 319 udelay(10); 320 321 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_CLR); 322 udelay(10); 323 } 324 325 static void apu_pcu_init(void) 326 { 327 uint32_t vapu_en_offset = BUCK_VAPU_PMIC_REG_EN_ADDR; 328 uint32_t vapu_sram_en_offset = BUCK_VAPU_SRAM_PMIC_REG_EN_ADDR; 329 330 mmio_write_32(APU_PCU_BASE + APU_PCU_CTRL_SET, AUTO_BUCK_EN); 331 332 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_STEP_SEL, BUCK_ON_OFF_CMD_EN); 333 334 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT0_L, 335 ((vapu_sram_en_offset << BUCK_OFFSET_SFT) + BUCK_ON_CMD)); 336 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT0_H, CMD_OP); 337 338 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT1_L, 339 ((vapu_en_offset << BUCK_OFFSET_SFT) + BUCK_ON_CMD)); 340 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT1_H, CMD_OP); 341 342 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT0_L, 343 ((vapu_en_offset << BUCK_OFFSET_SFT) + BUCK_OFF_CMD)); 344 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT0_H, CMD_OP); 345 346 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT1_L, 347 ((vapu_sram_en_offset << BUCK_OFFSET_SFT) + BUCK_OFF_CMD)); 348 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT1_H, CMD_OP); 349 350 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_SLE0, APU_PCU_BUCK_ON_SETTLE_TIME); 351 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_SLE1, APU_PCU_BUCK_ON_SETTLE_TIME); 352 } 353 354 static void apu_rpclite_init(void) 355 { 356 const uint32_t sleep_type_offset[] = { 357 APU_RPC_SW_TYPE2, 358 APU_RPC_SW_TYPE3, 359 APU_RPC_SW_TYPE4, 360 APU_RPC_SW_TYPE5, 361 APU_RPC_SW_TYPE6, 362 APU_RPC_SW_TYPE7, 363 APU_RPC_SW_TYPE8, 364 APU_RPC_SW_TYPE9 365 }; 366 int ofs_arr_size = ARRAY_SIZE(sleep_type_offset); 367 int ofs_idx; 368 369 for (ofs_idx = 0 ; ofs_idx < ofs_arr_size ; ofs_idx++) { 370 mmio_clrbits_32(APU_ACX0_RPC_LITE_BASE + sleep_type_offset[ofs_idx], 371 SW_TYPE); 372 } 373 374 mmio_setbits_32(APU_ACX0_RPC_LITE_BASE + APU_RPC_TOP_SEL, RPC_CTRL); 375 } 376 377 static void apu_rpc_init(void) 378 { 379 mmio_clrbits_32(APU_RPC_BASE + APU_RPC_SW_TYPE0, SW_TYPE); 380 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, RPC_TOP_CTRL); 381 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, RPC_TOP_CTRL1); 382 } 383 384 static int apu_are_init(void) 385 { 386 int ret; 387 int are_id = 0; 388 const uint32_t are_base[APU_ARE_NUM] = { APU_ARE0_BASE, APU_ARE1_BASE, APU_ARE2_BASE }; 389 const uint32_t are_entry2_cfg_l[APU_ARE_NUM] = { 390 ARE0_ENTRY2_CFG_L, 391 ARE1_ENTRY2_CFG_L, 392 ARE2_ENTRY2_CFG_L 393 }; 394 395 mmio_setbits_32(APU_AO_CTL_BASE + CSR_DUMMY_0_ADDR, VCORE_ARE_REQ); 396 397 ret = apu_poll(APU_ARE2_BASE + APU_ARE_GLO_FSM, ARE_GLO_FSM_IDLE, ARE_GLO_FSM_IDLE, 398 APU_ARE_POLLING_TIMEOUT_US); 399 if (ret != 0) { 400 ERROR(MODULE_TAG "[%s][%d] ARE init timeout\n", 401 __func__, __LINE__); 402 return ret; 403 } 404 405 for (are_id = APU_ARE0; are_id < APU_ARE_NUM; are_id++) { 406 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY0_SRAM_H, ARE_ENTRY0_SRAM_H_INIT); 407 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY0_SRAM_L, ARE_ENTRY0_SRAM_L_INIT); 408 409 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY1_SRAM_H, ARE_ENTRY1_SRAM_H_INIT); 410 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY1_SRAM_L, ARE_ENTRY1_SRAM_L_INIT); 411 412 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_H, ARE_ENTRY_CFG_H); 413 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_L, are_entry2_cfg_l[are_id]); 414 415 mmio_read_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_H); 416 mmio_read_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_L); 417 418 mmio_write_32(are_base[are_id] + APU_ARE_INI_CTRL, ARE_CONFG_INI); 419 } 420 421 return ret; 422 } 423 424 static void apu_aoc_init(void) 425 { 426 mmio_clrbits_32(SPM_BASE + APUSYS_BUCK_ISOLATION, IPU_EXT_BUCK_ISO); 427 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_CLR); 428 udelay(10); 429 430 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_SET); 431 udelay(10); 432 433 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_CLR); 434 udelay(10); 435 436 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, SRAM_AOC_ISO_CLR); 437 udelay(10); 438 } 439 440 static int init_hw_setting(void) 441 { 442 int ret; 443 444 apu_aoc_init(); 445 apu_pcu_init(); 446 apu_rpc_init(); 447 apu_rpclite_init(); 448 449 ret = apu_are_init(); 450 if (ret != 0) { 451 return ret; 452 } 453 454 apu_pll_init(); 455 apu_acc_init(); 456 apu_buck_off_cfg(); 457 458 return ret; 459 } 460 461 int apusys_power_init(void) 462 { 463 int ret; 464 465 ret = init_hw_setting(); 466 if (ret != 0) { 467 ERROR(MODULE_TAG "%s initial fail\n", __func__); 468 } else { 469 INFO(MODULE_TAG "%s initial done\n", __func__); 470 } 471 472 return ret; 473 } 474