1 /* 2 * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <inttypes.h> 8 9 /* TF-A system header */ 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/spinlock.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 17 /* Vendor header */ 18 #include "apusys.h" 19 #include "apusys_power.h" 20 #include "apusys_rv.h" 21 #include <mtk_mmap_pool.h> 22 23 static spinlock_t apu_lock; 24 static bool apusys_top_on; 25 26 static int apu_poll(uintptr_t reg, uint32_t mask, uint32_t value, uint32_t timeout_us) 27 { 28 uint32_t reg_val, count; 29 30 count = timeout_us / APU_POLL_STEP_US; 31 if (count == 0) { 32 count = 1; 33 } 34 35 do { 36 reg_val = mmio_read_32(reg); 37 if ((reg_val & mask) == value) { 38 return 0; 39 } 40 udelay(APU_POLL_STEP_US); 41 } while (--count); 42 43 ERROR(MODULE_TAG "Timeout polling APU register %#" PRIxPTR "\n", reg); 44 ERROR(MODULE_TAG "Read value 0x%x, expected 0x%x\n", reg_val, 45 (value == 0U) ? (reg_val & ~mask) : (reg_val | mask)); 46 47 return -1; 48 } 49 50 static void apu_backup_restore(enum APU_BACKUP_RESTORE_CTRL ctrl) 51 { 52 int i; 53 static struct apu_restore_data apu_restore_data[] = { 54 { UP_NORMAL_DOMAIN_NS, 0 }, 55 { UP_PRI_DOMAIN_NS, 0 }, 56 { UP_IOMMU_CTRL, 0 }, 57 { UP_CORE0_VABASE0, 0 }, 58 { UP_CORE0_MVABASE0, 0 }, 59 { UP_CORE0_VABASE1, 0 }, 60 { UP_CORE0_MVABASE1, 0 }, 61 { UP_CORE0_VABASE2, 0 }, 62 { UP_CORE0_MVABASE2, 0 }, 63 { UP_CORE0_VABASE3, 0 }, 64 { UP_CORE0_MVABASE3, 0 }, 65 { MD32_SYS_CTRL, 0 }, 66 { MD32_CLK_CTRL, 0 }, 67 { UP_WAKE_HOST_MASK0, 0 } 68 }; 69 70 switch (ctrl) { 71 case APU_CTRL_BACKUP: 72 for (i = 0; i < ARRAY_SIZE(apu_restore_data); i++) { 73 apu_restore_data[i].data = mmio_read_32(apu_restore_data[i].reg); 74 } 75 break; 76 case APU_CTRL_RESTORE: 77 for (i = 0; i < ARRAY_SIZE(apu_restore_data); i++) { 78 mmio_write_32(apu_restore_data[i].reg, apu_restore_data[i].data); 79 } 80 break; 81 default: 82 ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, ctrl); 83 break; 84 } 85 } 86 87 static void apu_xpu2apusys_d4_slv_en(enum APU_D4_SLV_CTRL en) 88 { 89 switch (en) { 90 case D4_SLV_OFF: 91 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0, 92 INFRA_FMEM_BUS_u_SI21_CTRL_EN); 93 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0, 94 INFRA_FMEM_BUS_u_SI22_CTRL_EN); 95 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0, 96 INFRA_FMEM_BUS_u_SI11_CTRL_EN); 97 mmio_setbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0, 98 INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN); 99 break; 100 case D4_SLV_ON: 101 mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI21_CTRL_0, 102 INFRA_FMEM_BUS_u_SI21_CTRL_EN); 103 mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI22_CTRL_0, 104 INFRA_FMEM_BUS_u_SI22_CTRL_EN); 105 mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_BUS_u_SI11_CTRL_0, 106 INFRA_FMEM_BUS_u_SI11_CTRL_EN); 107 mmio_clrbits_32(BCRM_FMEM_PDN_BASE + INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0, 108 INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN); 109 break; 110 default: 111 ERROR(MODULE_TAG "%s invalid op: %d\n", __func__, en); 112 break; 113 } 114 } 115 116 static void apu_pwr_flow_remote_sync(uint32_t cfg) 117 { 118 mmio_write_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG, (cfg & 0x1)); 119 } 120 121 int apusys_kernel_apusys_pwr_top_on(void) 122 { 123 int ret; 124 125 spin_lock(&apu_lock); 126 127 if (apusys_top_on == true) { 128 INFO(MODULE_TAG "%s: APUSYS already powered on!\n", __func__); 129 spin_unlock(&apu_lock); 130 return 0; 131 } 132 133 apu_pwr_flow_remote_sync(1); 134 135 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, AFC_ENA); 136 137 mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_SET); 138 139 ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY, 140 PWR_RDY, PWR_RDY, APU_TOP_ON_POLLING_TIMEOUT_US); 141 if (ret != 0) { 142 ERROR(MODULE_TAG "%s polling RPC RDY timeout, ret %d\n", __func__, ret); 143 spin_unlock(&apu_lock); 144 return ret; 145 } 146 147 ret = apu_poll(APU_RPC_BASE + APU_RPC_STATUS, 148 RPC_STATUS_RDY, RPC_STATUS_RDY, APU_TOP_ON_POLLING_TIMEOUT_US); 149 if (ret != 0) { 150 ERROR(MODULE_TAG "%s polling ARE FSM timeout, ret %d\n", __func__, ret); 151 spin_unlock(&apu_lock); 152 return ret; 153 } 154 155 mmio_write_32(APU_VCORE_BASE + APUSYS_VCORE_CG_CLR, CG_CLR); 156 mmio_write_32(APU_RCX_BASE + APU_RCX_CG_CLR, CG_CLR); 157 158 apu_xpu2apusys_d4_slv_en(D4_SLV_OFF); 159 160 apu_backup_restore(APU_CTRL_RESTORE); 161 162 apusys_top_on = true; 163 164 spin_unlock(&apu_lock); 165 return ret; 166 } 167 168 static void apu_sleep_rpc_rcx(void) 169 { 170 mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_CLR); 171 dsb(); 172 udelay(10); 173 174 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, (RPC_CTRL | RSV10)); 175 dsb(); 176 udelay(10); 177 178 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, CLR_IRQ); 179 dsb(); 180 udelay(10); 181 182 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, SLEEP_REQ); 183 dsb(); 184 udelay(100); 185 } 186 187 int apusys_kernel_apusys_pwr_top_off(void) 188 { 189 int ret; 190 191 spin_lock(&apu_lock); 192 193 if (apusys_top_on == false) { 194 INFO(MODULE_TAG "%s: APUSYS already powered off!\n", __func__); 195 spin_unlock(&apu_lock); 196 return 0; 197 } 198 199 apu_backup_restore(APU_CTRL_BACKUP); 200 201 apu_xpu2apusys_d4_slv_en(D4_SLV_ON); 202 203 if (mmio_read_32(APU_MBOX0_BASE + PWR_FLOW_SYNC_REG) == 0) { 204 apu_pwr_flow_remote_sync(1); 205 } else { 206 apu_sleep_rpc_rcx(); 207 } 208 209 ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY, 210 PWR_RDY, PWR_OFF, APU_TOP_OFF_POLLING_TIMEOUT_US); 211 if (ret != 0) { 212 ERROR(MODULE_TAG "%s timeout to wait RPC sleep (val:%d), ret %d\n", 213 __func__, APU_TOP_OFF_POLLING_TIMEOUT_US, ret); 214 spin_unlock(&apu_lock); 215 return ret; 216 } 217 218 apusys_top_on = false; 219 220 spin_unlock(&apu_lock); 221 return ret; 222 } 223 224 static void get_pll_pcw(const uint32_t clk_rate, uint32_t *r1, uint32_t *r2) 225 { 226 unsigned int fvco = clk_rate; 227 unsigned int pcw_val; 228 unsigned int postdiv_val = 1; 229 unsigned int postdiv_reg = 0; 230 231 while (fvco <= OUT_CLK_FREQ_MIN) { 232 postdiv_val = postdiv_val << 1; 233 postdiv_reg = postdiv_reg + 1; 234 fvco = fvco << 1; 235 } 236 237 pcw_val = (fvco * (1 << DDS_SHIFT)) / BASIC_CLK_FREQ; 238 239 if (postdiv_reg == 0) { 240 pcw_val = pcw_val * 2; 241 postdiv_val = postdiv_val << 1; 242 postdiv_reg = postdiv_reg + 1; 243 } 244 245 *r1 = postdiv_reg; 246 *r2 = pcw_val; 247 } 248 249 static void apu_pll_init(void) 250 { 251 const uint32_t pll_hfctl_cfg[PLL_NUM] = { 252 PLL4HPLL_FHCTL0_CFG, 253 PLL4HPLL_FHCTL1_CFG, 254 PLL4HPLL_FHCTL2_CFG, 255 PLL4HPLL_FHCTL3_CFG 256 }; 257 const uint32_t pll_con1[PLL_NUM] = { 258 PLL4H_PLL1_CON1, 259 PLL4H_PLL2_CON1, 260 PLL4H_PLL3_CON1, 261 PLL4H_PLL4_CON1 262 }; 263 const uint32_t pll_fhctl_dds[PLL_NUM] = { 264 PLL4HPLL_FHCTL0_DDS, 265 PLL4HPLL_FHCTL1_DDS, 266 PLL4HPLL_FHCTL2_DDS, 267 PLL4HPLL_FHCTL3_DDS 268 }; 269 const uint32_t pll_freq_out[PLL_NUM] = { 270 APUPLL0_DEFAULT_FREQ, 271 APUPLL1_DEFAULT_FREQ, 272 APUPLL2_DEFAULT_FREQ, 273 APUPLL3_DEFAULT_FREQ 274 }; 275 uint32_t pcw_val, posdiv_val; 276 int pll_idx; 277 278 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_RST_CON, PLL4H_PLL_HP_SWRSTB); 279 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_HP_EN, PLL4H_PLL_HP_EN); 280 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_CLK_CON, PLL4H_PLL_HP_CLKEN); 281 282 for (pll_idx = 0; pll_idx < PLL_NUM; pll_idx++) { 283 mmio_setbits_32(APU_PLL_BASE + pll_hfctl_cfg[pll_idx], (FHCTL0_EN | SFSTR0_EN)); 284 285 posdiv_val = 0; 286 pcw_val = 0; 287 get_pll_pcw(pll_freq_out[pll_idx], &posdiv_val, &pcw_val); 288 289 mmio_clrsetbits_32(APU_PLL_BASE + pll_con1[pll_idx], 290 (RG_PLL_POSDIV_MASK << RG_PLL_POSDIV_SFT), 291 (posdiv_val << RG_PLL_POSDIV_SFT)); 292 mmio_write_32(APU_PLL_BASE + pll_fhctl_dds[pll_idx], 293 (FHCTL_PLL_TGL_ORG | pcw_val)); 294 } 295 } 296 297 static void apu_acc_init(void) 298 { 299 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR0, CGEN_SOC); 300 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET0, HW_CTRL_EN); 301 302 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR1, CGEN_SOC); 303 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET1, HW_CTRL_EN); 304 305 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR2, CGEN_SOC); 306 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET2, HW_CTRL_EN); 307 mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET2, CLK_REQ_SW_EN); 308 309 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR3, CGEN_SOC); 310 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET3, HW_CTRL_EN); 311 mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET3, CLK_REQ_SW_EN); 312 313 mmio_write_32(APU_ACC_BASE + APU_ACC_CLK_INV_EN_SET, CLK_INV_EN); 314 } 315 316 static void apu_buck_off_cfg(void) 317 { 318 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_SET); 319 dsb(); 320 udelay(10); 321 322 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_SET); 323 dsb(); 324 udelay(10); 325 326 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_CLR); 327 dsb(); 328 udelay(10); 329 } 330 331 static void apu_pcu_init(void) 332 { 333 uint32_t vapu_en_offset = BUCK_VAPU_PMIC_REG_EN_ADDR; 334 uint32_t vapu_sram_en_offset = BUCK_VAPU_SRAM_PMIC_REG_EN_ADDR; 335 336 mmio_write_32(APU_PCU_BASE + APU_PCU_CTRL_SET, AUTO_BUCK_EN); 337 338 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_STEP_SEL, BUCK_ON_OFF_CMD_EN); 339 340 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT0_L, 341 ((vapu_sram_en_offset << BUCK_OFFSET_SFT) + BUCK_ON_CMD)); 342 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT0_H, CMD_OP); 343 344 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT1_L, 345 ((vapu_en_offset << BUCK_OFFSET_SFT) + BUCK_ON_CMD)); 346 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT1_H, CMD_OP); 347 348 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT0_L, 349 ((vapu_en_offset << BUCK_OFFSET_SFT) + BUCK_OFF_CMD)); 350 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT0_H, CMD_OP); 351 352 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT1_L, 353 ((vapu_sram_en_offset << BUCK_OFFSET_SFT) + BUCK_OFF_CMD)); 354 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT1_H, CMD_OP); 355 356 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_SLE0, APU_PCU_BUCK_ON_SETTLE_TIME); 357 mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_SLE1, APU_PCU_BUCK_ON_SETTLE_TIME); 358 } 359 360 static void apu_rpclite_init(void) 361 { 362 const uint32_t sleep_type_offset[] = { 363 APU_RPC_SW_TYPE2, 364 APU_RPC_SW_TYPE3, 365 APU_RPC_SW_TYPE4, 366 APU_RPC_SW_TYPE5, 367 APU_RPC_SW_TYPE6, 368 APU_RPC_SW_TYPE7, 369 APU_RPC_SW_TYPE8, 370 APU_RPC_SW_TYPE9 371 }; 372 int ofs_arr_size = ARRAY_SIZE(sleep_type_offset); 373 int ofs_idx; 374 375 for (ofs_idx = 0 ; ofs_idx < ofs_arr_size ; ofs_idx++) { 376 mmio_clrbits_32(APU_ACX0_RPC_LITE_BASE + sleep_type_offset[ofs_idx], 377 SW_TYPE); 378 } 379 380 mmio_setbits_32(APU_ACX0_RPC_LITE_BASE + APU_RPC_TOP_SEL, RPC_CTRL); 381 } 382 383 static void apu_rpc_init(void) 384 { 385 mmio_clrbits_32(APU_RPC_BASE + APU_RPC_SW_TYPE0, SW_TYPE); 386 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, RPC_TOP_CTRL); 387 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, RPC_TOP_CTRL1); 388 } 389 390 static int apu_are_init(void) 391 { 392 int ret; 393 int are_id = 0; 394 const uint32_t are_base[APU_ARE_NUM] = { APU_ARE0_BASE, APU_ARE1_BASE, APU_ARE2_BASE }; 395 const uint32_t are_entry2_cfg_l[APU_ARE_NUM] = { 396 ARE0_ENTRY2_CFG_L, 397 ARE1_ENTRY2_CFG_L, 398 ARE2_ENTRY2_CFG_L 399 }; 400 401 mmio_setbits_32(APU_AO_CTL_BASE + CSR_DUMMY_0_ADDR, VCORE_ARE_REQ); 402 403 ret = apu_poll(APU_ARE2_BASE + APU_ARE_GLO_FSM, ARE_GLO_FSM_IDLE, ARE_GLO_FSM_IDLE, 404 APU_ARE_POLLING_TIMEOUT_US); 405 if (ret != 0) { 406 ERROR(MODULE_TAG "[%s][%d] ARE init timeout\n", 407 __func__, __LINE__); 408 return ret; 409 } 410 411 for (are_id = APU_ARE0; are_id < APU_ARE_NUM; are_id++) { 412 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY0_SRAM_H, ARE_ENTRY0_SRAM_H_INIT); 413 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY0_SRAM_L, ARE_ENTRY0_SRAM_L_INIT); 414 415 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY1_SRAM_H, ARE_ENTRY1_SRAM_H_INIT); 416 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY1_SRAM_L, ARE_ENTRY1_SRAM_L_INIT); 417 418 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_H, ARE_ENTRY_CFG_H); 419 mmio_write_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_L, are_entry2_cfg_l[are_id]); 420 421 mmio_read_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_H); 422 mmio_read_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_L); 423 424 mmio_write_32(are_base[are_id] + APU_ARE_INI_CTRL, ARE_CONFG_INI); 425 } 426 427 return ret; 428 } 429 430 static void apu_aoc_init(void) 431 { 432 mmio_clrbits_32(SPM_BASE + APUSYS_BUCK_ISOLATION, IPU_EXT_BUCK_ISO); 433 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_CLR); 434 dsb(); 435 udelay(10); 436 437 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_SET); 438 dsb(); 439 udelay(10); 440 441 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_CLR); 442 dsb(); 443 udelay(10); 444 445 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, SRAM_AOC_ISO_CLR); 446 dsb(); 447 udelay(10); 448 } 449 450 static int init_hw_setting(void) 451 { 452 int ret; 453 454 apu_aoc_init(); 455 apu_pcu_init(); 456 apu_rpc_init(); 457 apu_rpclite_init(); 458 459 ret = apu_are_init(); 460 if (ret != 0) { 461 return ret; 462 } 463 464 apu_pll_init(); 465 apu_acc_init(); 466 apu_buck_off_cfg(); 467 468 return ret; 469 } 470 471 int apusys_power_init(void) 472 { 473 int ret; 474 475 ret = init_hw_setting(); 476 if (ret != 0) { 477 ERROR(MODULE_TAG "%s initial fail\n", __func__); 478 } else { 479 INFO(MODULE_TAG "%s initial done\n", __func__); 480 } 481 482 return ret; 483 } 484