1 /* 2 * Copyright (c) 2023-2024, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* TF-A system header */ 8 #include <common/debug.h> 9 #include <drivers/delay_timer.h> 10 #include <lib/mmio.h> 11 #include <lib/spinlock.h> 12 13 /* Vendor header */ 14 #include "apusys.h" 15 #include "apusys_rv.h" 16 #include "apusys_rv_mbox_mpu.h" 17 #include "apusys_rv_pwr_ctrl.h" 18 #include "emi_mpu.h" 19 20 static spinlock_t apusys_rv_lock; 21 22 void apusys_rv_mbox_mpu_init(void) 23 { 24 int i; 25 26 for (i = 0; i < APU_MBOX_NUM; i++) { 27 mmio_write_32(APU_MBOX_FUNC_CFG(i), 28 (MBOX_CTRL_LOCK | 29 (mbox_mpu_setting_tab[i].no_mpu << MBOX_NO_MPU_SHIFT))); 30 mmio_write_32(APU_MBOX_DOMAIN_CFG(i), 31 (MBOX_CTRL_LOCK | 32 (mbox_mpu_setting_tab[i].rx_ns << MBOX_RX_NS_SHIFT) | 33 (mbox_mpu_setting_tab[i].rx_domain << MBOX_RX_DOMAIN_SHIFT) | 34 (mbox_mpu_setting_tab[i].tx_ns << MBOX_TX_NS_SHIFT) | 35 (mbox_mpu_setting_tab[i].tx_domain << MBOX_TX_DOMAIN_SHIFT))); 36 } 37 } 38 39 int apusys_kernel_apusys_rv_setup_reviser(void) 40 { 41 spin_lock(&apusys_rv_lock); 42 43 mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL); 44 mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL); 45 46 mmio_write_32(UP_IOMMU_CTRL, MMU_CTRL_LOCK | MMU_CTRL | MMU_EN); 47 48 mmio_write_32(UP_NORMAL_DOMAIN_NS, 49 (UP_NORMAL_DOMAIN << UP_DOMAIN_SHIFT) | (UP_NORMAL_NS << UP_NS_SHIFT)); 50 mmio_write_32(UP_PRI_DOMAIN_NS, 51 (UP_PRI_DOMAIN << UP_DOMAIN_SHIFT) | (UP_PRI_NS << UP_NS_SHIFT)); 52 53 mmio_write_32(UP_CORE0_VABASE0, 54 VLD | PARTIAL_ENABLE | (THREAD_NUM_PRI << THREAD_NUM_SHIFT)); 55 mmio_write_32(UP_CORE0_MVABASE0, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT)); 56 57 mmio_write_32(UP_CORE0_VABASE1, 58 VLD | PARTIAL_ENABLE | (THREAD_NUM_NORMAL << THREAD_NUM_SHIFT)); 59 mmio_write_32(UP_CORE0_MVABASE1, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT)); 60 61 spin_unlock(&apusys_rv_lock); 62 63 return 0; 64 } 65 66 int apusys_kernel_apusys_rv_reset_mp(void) 67 { 68 spin_lock(&apusys_rv_lock); 69 70 mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST); 71 72 dsb(); 73 udelay(RESET_DEALY_US); 74 75 mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN | 76 MD32_DM_ARUSER_IOMMU_EN | MD32_PM_AWUSER_IOMMU_EN | MD32_PM_ARUSER_IOMMU_EN | 77 MD32_SOFT_RSTN); 78 79 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN); 80 mmio_write_32(UP_WAKE_HOST_MASK0, WDT_IRQ_EN); 81 mmio_write_32(UP_WAKE_HOST_MASK1, MBOX0_IRQ_EN | MBOX1_IRQ_EN | MBOX2_IRQ_EN); 82 83 spin_unlock(&apusys_rv_lock); 84 85 return 0; 86 } 87 88 int apusys_kernel_apusys_rv_setup_boot(void) 89 { 90 spin_lock(&apusys_rv_lock); 91 92 mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA); 93 94 mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) | 95 (PREDEFINE_CACHE << PREDEF_2G_OFS) | (PREDEFINE_CACHE << PREDEF_3G_OFS) | 96 (PREDEFINE_CACHE << PREDEF_4G_OFS)); 97 98 spin_unlock(&apusys_rv_lock); 99 return 0; 100 } 101 102 int apusys_kernel_apusys_rv_start_mp(void) 103 { 104 spin_lock(&apusys_rv_lock); 105 mmio_write_32(MD32_RUNSTALL, MD32_RUN); 106 spin_unlock(&apusys_rv_lock); 107 108 return 0; 109 } 110 111 int apusys_kernel_apusys_rv_stop_mp(void) 112 { 113 spin_lock(&apusys_rv_lock); 114 mmio_write_32(MD32_RUNSTALL, MD32_STALL); 115 spin_unlock(&apusys_rv_lock); 116 117 return 0; 118 } 119 120 int apusys_kernel_apusys_rv_setup_sec_mem(void) 121 { 122 int ret; 123 124 spin_lock(&apusys_rv_lock); 125 126 ret = set_apu_emi_mpu_region(); 127 if (ret != 0) { 128 ERROR(MODULE_TAG "%s: set emimpu protection failed\n", __func__); 129 } 130 131 spin_unlock(&apusys_rv_lock); 132 return ret; 133 } 134 135 int apusys_kernel_apusys_rv_disable_wdt_isr(void) 136 { 137 spin_lock(&apusys_rv_lock); 138 mmio_clrbits_32(WDT_CTRL0, WDT_EN); 139 spin_unlock(&apusys_rv_lock); 140 141 return 0; 142 } 143 144 int apusys_kernel_apusys_rv_clear_wdt_isr(void) 145 { 146 spin_lock(&apusys_rv_lock); 147 mmio_clrbits_32(UP_INT_EN2, DBG_APB_EN); 148 mmio_write_32(WDT_INT, WDT_INT_W1C); 149 spin_unlock(&apusys_rv_lock); 150 151 return 0; 152 } 153 154 int apusys_kernel_apusys_rv_cg_gating(void) 155 { 156 spin_lock(&apusys_rv_lock); 157 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS); 158 spin_unlock(&apusys_rv_lock); 159 160 return 0; 161 } 162 163 int apusys_kernel_apusys_rv_cg_ungating(void) 164 { 165 spin_lock(&apusys_rv_lock); 166 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN); 167 spin_unlock(&apusys_rv_lock); 168 169 return 0; 170 } 171