1 /* 2 * Copyright (c) 2023-2024, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* TF-A system header */ 8 #include <common/debug.h> 9 #include <drivers/delay_timer.h> 10 #include <lib/mmio.h> 11 #include <lib/spinlock.h> 12 13 /* Vendor header */ 14 #include "apusys.h" 15 #include "apusys_rv.h" 16 #include "apusys_rv_mbox_mpu.h" 17 #include "apusys_rv_pwr_ctrl.h" 18 #include "emi_mpu.h" 19 20 #ifdef CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT 21 #include "apusys_ammu.h" 22 #endif 23 24 static spinlock_t apusys_rv_lock; 25 26 void apusys_rv_mbox_mpu_init(void) 27 { 28 int i; 29 30 for (i = 0; i < APU_MBOX_NUM; i++) { 31 mmio_write_32(APU_MBOX_FUNC_CFG(i), 32 (MBOX_CTRL_LOCK | 33 (mbox_mpu_setting_tab[i].no_mpu << MBOX_NO_MPU_SHIFT))); 34 mmio_write_32(APU_MBOX_DOMAIN_CFG(i), 35 (MBOX_CTRL_LOCK | 36 (mbox_mpu_setting_tab[i].rx_ns << MBOX_RX_NS_SHIFT) | 37 (mbox_mpu_setting_tab[i].rx_domain << MBOX_RX_DOMAIN_SHIFT) | 38 (mbox_mpu_setting_tab[i].tx_ns << MBOX_TX_NS_SHIFT) | 39 (mbox_mpu_setting_tab[i].tx_domain << MBOX_TX_DOMAIN_SHIFT))); 40 } 41 } 42 43 int apusys_kernel_apusys_rv_setup_reviser(void) 44 { 45 spin_lock(&apusys_rv_lock); 46 47 mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL); 48 mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL); 49 50 mmio_write_32(UP_IOMMU_CTRL, MMU_CTRL_LOCK | MMU_CTRL | MMU_EN); 51 52 mmio_write_32(UP_NORMAL_DOMAIN_NS, 53 (UP_NORMAL_DOMAIN << UP_DOMAIN_SHIFT) | (UP_NORMAL_NS << UP_NS_SHIFT)); 54 mmio_write_32(UP_PRI_DOMAIN_NS, 55 (UP_PRI_DOMAIN << UP_DOMAIN_SHIFT) | (UP_PRI_NS << UP_NS_SHIFT)); 56 57 mmio_write_32(UP_CORE0_VABASE0, 58 VLD | PARTIAL_ENABLE | (THREAD_NUM_PRI << THREAD_NUM_SHIFT)); 59 mmio_write_32(UP_CORE0_MVABASE0, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT)); 60 61 mmio_write_32(UP_CORE0_VABASE1, 62 VLD | PARTIAL_ENABLE | (THREAD_NUM_NORMAL << THREAD_NUM_SHIFT)); 63 mmio_write_32(UP_CORE0_MVABASE1, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT)); 64 65 spin_unlock(&apusys_rv_lock); 66 67 return 0; 68 } 69 70 int apusys_kernel_apusys_rv_reset_mp(void) 71 { 72 spin_lock(&apusys_rv_lock); 73 74 mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST); 75 76 dsb(); 77 udelay(RESET_DEALY_US); 78 79 mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN | 80 MD32_DM_ARUSER_IOMMU_EN | MD32_PM_AWUSER_IOMMU_EN | MD32_PM_ARUSER_IOMMU_EN | 81 MD32_SOFT_RSTN); 82 83 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN); 84 mmio_write_32(UP_WAKE_HOST_MASK0, WDT_IRQ_EN); 85 mmio_write_32(UP_WAKE_HOST_MASK1, MBOX0_IRQ_EN | MBOX1_IRQ_EN | MBOX2_IRQ_EN); 86 87 spin_unlock(&apusys_rv_lock); 88 89 return 0; 90 } 91 92 int apusys_kernel_apusys_rv_setup_boot(void) 93 { 94 spin_lock(&apusys_rv_lock); 95 96 mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA); 97 98 mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) | 99 (PREDEFINE_CACHE << PREDEF_2G_OFS) | (PREDEFINE_CACHE << PREDEF_3G_OFS) | 100 (PREDEFINE_CACHE << PREDEF_4G_OFS)); 101 102 apusys_infra_dcm_setup(); 103 104 spin_unlock(&apusys_rv_lock); 105 return 0; 106 } 107 108 int apusys_kernel_apusys_rv_start_mp(void) 109 { 110 spin_lock(&apusys_rv_lock); 111 mmio_write_32(MD32_RUNSTALL, MD32_RUN); 112 spin_unlock(&apusys_rv_lock); 113 114 return 0; 115 } 116 117 int apusys_kernel_apusys_rv_stop_mp(void) 118 { 119 spin_lock(&apusys_rv_lock); 120 mmio_write_32(MD32_RUNSTALL, MD32_STALL); 121 spin_unlock(&apusys_rv_lock); 122 123 return 0; 124 } 125 126 int apusys_kernel_apusys_rv_setup_sec_mem(void) 127 { 128 int ret; 129 130 spin_lock(&apusys_rv_lock); 131 132 ret = set_apu_emi_mpu_region(); 133 if (ret != 0) { 134 ERROR(MODULE_TAG "%s: set emimpu protection failed\n", __func__); 135 } 136 137 spin_unlock(&apusys_rv_lock); 138 return ret; 139 } 140 141 int apusys_kernel_apusys_rv_disable_wdt_isr(void) 142 { 143 spin_lock(&apusys_rv_lock); 144 mmio_clrbits_32(WDT_CTRL0, WDT_EN); 145 spin_unlock(&apusys_rv_lock); 146 147 return 0; 148 } 149 150 int apusys_kernel_apusys_rv_clear_wdt_isr(void) 151 { 152 spin_lock(&apusys_rv_lock); 153 mmio_clrbits_32(UP_INT_EN2, DBG_APB_EN); 154 mmio_write_32(WDT_INT, WDT_INT_W1C); 155 spin_unlock(&apusys_rv_lock); 156 157 return 0; 158 } 159 160 int apusys_kernel_apusys_rv_cg_gating(void) 161 { 162 spin_lock(&apusys_rv_lock); 163 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS); 164 spin_unlock(&apusys_rv_lock); 165 166 return 0; 167 } 168 169 int apusys_kernel_apusys_rv_cg_ungating(void) 170 { 171 spin_lock(&apusys_rv_lock); 172 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN); 173 spin_unlock(&apusys_rv_lock); 174 175 return 0; 176 } 177 178 int apusys_kernel_apusys_rv_setup_apummu(void) 179 { 180 spin_lock(&apusys_rv_lock); 181 182 #ifdef CONFIG_MTK_APUSYS_SEC_CTRL 183 sec_set_rv_dns(); 184 #endif 185 186 #ifdef CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT 187 uint32_t apummu_tcm_sz_select = 0; 188 189 if (APU_MD32_TCM_SZ <= 0x20000) 190 apummu_tcm_sz_select = APUMMU_PAGE_LEN_128KB; 191 else if (APU_MD32_TCM_SZ <= 0x40000) 192 apummu_tcm_sz_select = APUMMU_PAGE_LEN_256KB; 193 else if (APU_MD32_TCM_SZ <= 0x80000) 194 apummu_tcm_sz_select = APUMMU_PAGE_LEN_512KB; 195 else if (APU_MD32_TCM_SZ <= 0x100000) 196 apummu_tcm_sz_select = APUMMU_PAGE_LEN_1MB; 197 else { 198 ERROR("%s: APU_MD32_TCM_SZ = 0x%x > 1MB", __func__, APU_MD32_TCM_SZ); 199 spin_unlock(&apusys_rv_lock); 200 return -EINVAL; 201 } 202 203 INFO("%s: apummu_tcm_sz_select = %u\n", __func__, apummu_tcm_sz_select); 204 rv_boot(APU_SEC_FW_IOVA, 0, APUMMU_PAGE_LEN_1MB, 205 APU_MD32_TCM, apummu_tcm_sz_select); 206 #endif 207 208 spin_unlock(&apusys_rv_lock); 209 return 0; 210 } 211 212 int apusys_kernel_apusys_rv_pwr_ctrl(enum APU_PWR_OP op) 213 { 214 return apusys_rv_pwr_ctrl(op); 215 } 216