xref: /rk3399_ARM-atf/plat/mediatek/common/mtk_plat_common.c (revision cf906b2a2e017077d54bbe9111a099cd0cc59433)
1*cf906b2aSLeon Chen /*
2*cf906b2aSLeon Chen  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3*cf906b2aSLeon Chen  *
4*cf906b2aSLeon Chen  * Redistribution and use in source and binary forms, with or without
5*cf906b2aSLeon Chen  * modification, are permitted provided that the following conditions are met:
6*cf906b2aSLeon Chen  *
7*cf906b2aSLeon Chen  * Redistributions of source code must retain the above copyright notice, this
8*cf906b2aSLeon Chen  * list of conditions and the following disclaimer.
9*cf906b2aSLeon Chen  *
10*cf906b2aSLeon Chen  * Redistributions in binary form must reproduce the above copyright notice,
11*cf906b2aSLeon Chen  * this list of conditions and the following disclaimer in the documentation
12*cf906b2aSLeon Chen  * and/or other materials provided with the distribution.
13*cf906b2aSLeon Chen  *
14*cf906b2aSLeon Chen  * Neither the name of ARM nor the names of its contributors may be used
15*cf906b2aSLeon Chen  * to endorse or promote products derived from this software without specific
16*cf906b2aSLeon Chen  * prior written permission.
17*cf906b2aSLeon Chen  *
18*cf906b2aSLeon Chen  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19*cf906b2aSLeon Chen  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20*cf906b2aSLeon Chen  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21*cf906b2aSLeon Chen  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22*cf906b2aSLeon Chen  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23*cf906b2aSLeon Chen  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24*cf906b2aSLeon Chen  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25*cf906b2aSLeon Chen  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26*cf906b2aSLeon Chen  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27*cf906b2aSLeon Chen  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28*cf906b2aSLeon Chen  * POSSIBILITY OF SUCH DAMAGE.
29*cf906b2aSLeon Chen  */
30*cf906b2aSLeon Chen #include <arch_helpers.h>
31*cf906b2aSLeon Chen #include <arm_gic.h>
32*cf906b2aSLeon Chen #include <bl_common.h>
33*cf906b2aSLeon Chen #include <cci.h>
34*cf906b2aSLeon Chen #include <console.h>
35*cf906b2aSLeon Chen #include <debug.h>
36*cf906b2aSLeon Chen #include <mmio.h>
37*cf906b2aSLeon Chen #include <mtk_plat_common.h>
38*cf906b2aSLeon Chen #include <mtk_sip_svc.h>
39*cf906b2aSLeon Chen #include <platform.h>
40*cf906b2aSLeon Chen #include <plat_private.h>
41*cf906b2aSLeon Chen #include <xlat_tables.h>
42*cf906b2aSLeon Chen 
43*cf906b2aSLeon Chen struct atf_arg_t gteearg;
44*cf906b2aSLeon Chen 
45*cf906b2aSLeon Chen void clean_top_32b_of_param(uint32_t smc_fid,
46*cf906b2aSLeon Chen 				uint64_t *px1,
47*cf906b2aSLeon Chen 				uint64_t *px2,
48*cf906b2aSLeon Chen 				uint64_t *px3,
49*cf906b2aSLeon Chen 				uint64_t *px4)
50*cf906b2aSLeon Chen {
51*cf906b2aSLeon Chen 	/* if parameters from SMC32. Clean top 32 bits */
52*cf906b2aSLeon Chen 	if (0 == (smc_fid & SMC_AARCH64_BIT)) {
53*cf906b2aSLeon Chen 		*px1 = *px1 & SMC32_PARAM_MASK;
54*cf906b2aSLeon Chen 		*px2 = *px2 & SMC32_PARAM_MASK;
55*cf906b2aSLeon Chen 		*px3 = *px3 & SMC32_PARAM_MASK;
56*cf906b2aSLeon Chen 		*px4 = *px4 & SMC32_PARAM_MASK;
57*cf906b2aSLeon Chen 	}
58*cf906b2aSLeon Chen }
59*cf906b2aSLeon Chen 
60*cf906b2aSLeon Chen #if MTK_SIP_KERNEL_BOOT_ENABLE
61*cf906b2aSLeon Chen static struct kernel_info k_info;
62*cf906b2aSLeon Chen 
63*cf906b2aSLeon Chen static void save_kernel_info(uint64_t pc,
64*cf906b2aSLeon Chen 			uint64_t r0,
65*cf906b2aSLeon Chen 			uint64_t r1,
66*cf906b2aSLeon Chen 			uint64_t k32_64)
67*cf906b2aSLeon Chen {
68*cf906b2aSLeon Chen 	k_info.k32_64 = k32_64;
69*cf906b2aSLeon Chen 	k_info.pc = pc;
70*cf906b2aSLeon Chen 
71*cf906b2aSLeon Chen 	if (LINUX_KERNEL_32 ==  k32_64) {
72*cf906b2aSLeon Chen 		/* for 32 bits kernel */
73*cf906b2aSLeon Chen 		k_info.r0 = 0;
74*cf906b2aSLeon Chen 		/* machtype */
75*cf906b2aSLeon Chen 		k_info.r1 = r0;
76*cf906b2aSLeon Chen 		/* tags */
77*cf906b2aSLeon Chen 		k_info.r2 = r1;
78*cf906b2aSLeon Chen 	} else {
79*cf906b2aSLeon Chen 		/* for 64 bits kernel */
80*cf906b2aSLeon Chen 		k_info.r0 = r0;
81*cf906b2aSLeon Chen 		k_info.r1 = r1;
82*cf906b2aSLeon Chen 	}
83*cf906b2aSLeon Chen }
84*cf906b2aSLeon Chen 
85*cf906b2aSLeon Chen uint64_t get_kernel_info_pc(void)
86*cf906b2aSLeon Chen {
87*cf906b2aSLeon Chen 	return k_info.pc;
88*cf906b2aSLeon Chen }
89*cf906b2aSLeon Chen 
90*cf906b2aSLeon Chen uint64_t get_kernel_info_r0(void)
91*cf906b2aSLeon Chen {
92*cf906b2aSLeon Chen 	return k_info.r0;
93*cf906b2aSLeon Chen }
94*cf906b2aSLeon Chen 
95*cf906b2aSLeon Chen uint64_t get_kernel_info_r1(void)
96*cf906b2aSLeon Chen {
97*cf906b2aSLeon Chen 	return k_info.r1;
98*cf906b2aSLeon Chen }
99*cf906b2aSLeon Chen 
100*cf906b2aSLeon Chen uint64_t get_kernel_info_r2(void)
101*cf906b2aSLeon Chen {
102*cf906b2aSLeon Chen 	return k_info.r2;
103*cf906b2aSLeon Chen }
104*cf906b2aSLeon Chen 
105*cf906b2aSLeon Chen void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4)
106*cf906b2aSLeon Chen {
107*cf906b2aSLeon Chen 	static uint8_t kernel_boot_once_flag;
108*cf906b2aSLeon Chen 	/* only support in booting flow */
109*cf906b2aSLeon Chen 	if (0 == kernel_boot_once_flag) {
110*cf906b2aSLeon Chen 		kernel_boot_once_flag = 1;
111*cf906b2aSLeon Chen 
112*cf906b2aSLeon Chen 		console_init(gteearg.atf_log_port,
113*cf906b2aSLeon Chen 			UART_CLOCK, UART_BAUDRATE);
114*cf906b2aSLeon Chen 		INFO("save kernel info\n");
115*cf906b2aSLeon Chen 		save_kernel_info(x1, x2, x3, x4);
116*cf906b2aSLeon Chen 		bl31_prepare_kernel_entry(x4);
117*cf906b2aSLeon Chen 		INFO("el3_exit\n");
118*cf906b2aSLeon Chen 		console_uninit();
119*cf906b2aSLeon Chen 	}
120*cf906b2aSLeon Chen }
121*cf906b2aSLeon Chen #endif
122*cf906b2aSLeon Chen 
123*cf906b2aSLeon Chen uint32_t plat_get_spsr_for_bl33_entry(void)
124*cf906b2aSLeon Chen {
125*cf906b2aSLeon Chen 	unsigned int mode;
126*cf906b2aSLeon Chen 	uint32_t spsr;
127*cf906b2aSLeon Chen 	unsigned int ee;
128*cf906b2aSLeon Chen 	unsigned long daif;
129*cf906b2aSLeon Chen 
130*cf906b2aSLeon Chen 	INFO("Secondary bootloader is AArch32\n");
131*cf906b2aSLeon Chen 	mode = MODE32_svc;
132*cf906b2aSLeon Chen 	ee = 0;
133*cf906b2aSLeon Chen 	/*
134*cf906b2aSLeon Chen 	 * TODO: Choose async. exception bits if HYP mode is not
135*cf906b2aSLeon Chen 	 * implemented according to the values of SCR.{AW, FW} bits
136*cf906b2aSLeon Chen 	 */
137*cf906b2aSLeon Chen 	daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
138*cf906b2aSLeon Chen 
139*cf906b2aSLeon Chen 	spsr = SPSR_MODE32(mode, 0, ee, daif);
140*cf906b2aSLeon Chen 	return spsr;
141*cf906b2aSLeon Chen }
142