xref: /rk3399_ARM-atf/plat/mediatek/common/lpm_v2/mt_lp_api.c (revision 10ecd58093a34e95e2dfad65b1180610f29397cc)
1 /*
2  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <lpm_v2/mt_lp_api.h>
8 
9 #define UPDATE_STATUS(val, status, bit) \
10 	((val) ? ((status) | (1 << (bit))) : ((status) & ~(1 << (bit))))
11 
12 static uint64_t lp_status;
13 
14 int mt_audio_update(int type)
15 {
16 	int ret, val;
17 
18 	switch (type) {
19 	case AUDIO_AFE_ENTER:
20 	case AUDIO_AFE_LEAVE:
21 		val = (type == AUDIO_AFE_ENTER) ? 1 : 0;
22 		lp_status = UPDATE_STATUS(val, lp_status, AUDIO_AFE);
23 		ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_FMAUDIO, &val);
24 		break;
25 	case AUDIO_DSP_ENTER:
26 	case AUDIO_DSP_LEAVE:
27 		val = (type == AUDIO_DSP_ENTER) ? 1 : 0;
28 		lp_status = UPDATE_STATUS(val, lp_status, AUDIO_DSP);
29 		ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_ADSP, &val);
30 		break;
31 	default:
32 		ret = -1;
33 		break;
34 	}
35 
36 	return ret;
37 }
38 
39 int mt_usb_update(int type)
40 {
41 	int ret, val;
42 
43 	switch (type) {
44 	case LPM_USB_ENTER:
45 	case LPM_USB_LEAVE:
46 		val = (type == LPM_USB_ENTER) ? 1 : 0;
47 		ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_USB_INFRA, &val);
48 		break;
49 	case USB_HEADSET_ENTER:
50 	case USB_HEADSET_LEAVE:
51 		val = (type == USB_HEADSET_ENTER) ? 1 : 0;
52 		lp_status = UPDATE_STATUS(val, lp_status, USB_HEADSET);
53 		ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_USB_HEADSET, &val);
54 		break;
55 	default:
56 		ret = -1;
57 		break;
58 	}
59 
60 	return ret;
61 }
62 
63 uint64_t mt_get_lp_scenario_status(void)
64 {
65 	return lp_status;
66 }
67 
68 int mt_gpueb_hwctrl(int type, void *priv)
69 {
70 	int ret, val;
71 
72 	switch (type) {
73 	case GPUEB_PLL_EN:
74 	case GPUEB_PLL_DIS:
75 		val = (type == GPUEB_PLL_EN) ? 1 : 0;
76 		ret = mt_lp_rm_do_hwctrl(PLAT_AP_GPUEB_PLL_CONTROL, val, priv);
77 		break;
78 	case GPUEB_GET_PWR_STATUS:
79 		ret = mt_lp_rm_do_hwctrl(PLAT_AP_GPUEB_PWR_STATUS, 0, priv);
80 		break;
81 	case GPUEB_GET_MFG0_PWR_CON:
82 		ret = mt_lp_rm_do_hwctrl(PLAT_AP_GPUEB_MFG0_PWR_CON, 0, priv);
83 		break;
84 	default:
85 		ret = -1;
86 		break;
87 	}
88 
89 	return ret;
90 }
91