xref: /rk3399_ARM-atf/plat/mediatek/common/include/plat_macros.S (revision 6ffda26bd0b90ea62a254006947b5f616a6ebcea)
1*22090026SGavin Liu/*
2*22090026SGavin Liu * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3*22090026SGavin Liu *
4*22090026SGavin Liu * SPDX-License-Identifier: BSD-3-Clause
5*22090026SGavin Liu */
6*22090026SGavin Liu
7*22090026SGavin Liu#ifndef PLAT_MACROS_S
8*22090026SGavin Liu#define PLAT_MACROS_S
9*22090026SGavin Liu
10*22090026SGavin Liu#include <platform_def.h>
11*22090026SGavin Liu
12*22090026SGavin Liu.section .rodata.gic_reg_name, "aS"
13*22090026SGavin Liugicc_regs:
14*22090026SGavin Liu	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
15*22090026SGavin Liugicd_pend_reg:
16*22090026SGavin Liu	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
17*22090026SGavin Liu		" Offset:\t\t\tvalue\n"
18*22090026SGavin Liunewline:
19*22090026SGavin Liu	.asciz "\n"
20*22090026SGavin Liuspacer:
21*22090026SGavin Liu	.asciz ":\t\t0x"
22*22090026SGavin Liu
23*22090026SGavin Liu.section .rodata.cci_reg_name, "aS"
24*22090026SGavin Liucci_iface_regs:
25*22090026SGavin Liu	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
26*22090026SGavin Liu
27*22090026SGavin Liu	/* ---------------------------------------------
28*22090026SGavin Liu	 * The below macro prints out relevant GIC
29*22090026SGavin Liu	 * registers whenever an unhandled exception
30*22090026SGavin Liu	 * is taken in BL31.
31*22090026SGavin Liu	 * Clobbers: x0 - x10, x26, x27, sp
32*22090026SGavin Liu	 * ---------------------------------------------
33*22090026SGavin Liu	 */
34*22090026SGavin Liu	.macro plat_crash_print_regs
35*22090026SGavin Liu	/* TODO: leave implementation to GIC owner */
36*22090026SGavin Liu	.endm
37*22090026SGavin Liu
38*22090026SGavin Liu#endif /* PLAT_MACROS_S */
39