xref: /rk3399_ARM-atf/plat/mediatek/common/cache_ops.c (revision b660cdf9fdbf278927ccbe44f67640060c4fdc99)
1*7794e7c0SVince Liu /*
2*7794e7c0SVince Liu  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3*7794e7c0SVince Liu  *
4*7794e7c0SVince Liu  * SPDX-License-Identifier: BSD-3-Clause
5*7794e7c0SVince Liu  */
6*7794e7c0SVince Liu 
7*7794e7c0SVince Liu #include <arch_helpers.h>
8*7794e7c0SVince Liu #include <lib/mmio.h>
9*7794e7c0SVince Liu 
10*7794e7c0SVince Liu #include <cache_ops.h>
11*7794e7c0SVince Liu #include <mcucfg.h>
12*7794e7c0SVince Liu 
13*7794e7c0SVince Liu #define L3_SHARE_EN	9
14*7794e7c0SVince Liu #define L3_SHARE_PRE_EN	8
15*7794e7c0SVince Liu 
disable_cache_as_ram(void)16*7794e7c0SVince Liu void disable_cache_as_ram(void)
17*7794e7c0SVince Liu {
18*7794e7c0SVince Liu 	unsigned long v;
19*7794e7c0SVince Liu 
20*7794e7c0SVince Liu 	mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_EN);
21*7794e7c0SVince Liu 	dsb();
22*7794e7c0SVince Liu 
23*7794e7c0SVince Liu 	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
24*7794e7c0SVince Liu 	v |= (0xf << 4);
25*7794e7c0SVince Liu 	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
26*7794e7c0SVince Liu 	dsb();
27*7794e7c0SVince Liu 
28*7794e7c0SVince Liu 	do {
29*7794e7c0SVince Liu 		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
30*7794e7c0SVince Liu 	} while (((v >> 0x4) & 0xf) != 0xf);
31*7794e7c0SVince Liu 
32*7794e7c0SVince Liu 	mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_PRE_EN);
33*7794e7c0SVince Liu 	dsb();
34*7794e7c0SVince Liu }
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