1*a2847172SGrzegorz Jaszczyk /* 2*a2847172SGrzegorz Jaszczyk * Copyright (C) 2018 Marvell International Ltd. 3*a2847172SGrzegorz Jaszczyk * 4*a2847172SGrzegorz Jaszczyk * SPDX-License-Identifier: BSD-3-Clause 5*a2847172SGrzegorz Jaszczyk * https://spdx.org/licenses 6*a2847172SGrzegorz Jaszczyk */ 7*a2847172SGrzegorz Jaszczyk 8*a2847172SGrzegorz Jaszczyk #ifndef MSS_MEM_H 9*a2847172SGrzegorz Jaszczyk #define MSS_MEM_H 10*a2847172SGrzegorz Jaszczyk 11*a2847172SGrzegorz Jaszczyk /* MSS SRAM Memory base */ 12*a2847172SGrzegorz Jaszczyk #define MSS_SRAM_PM_CONTROL_BASE (MVEBU_REGS_BASE + 0x520000) 13*a2847172SGrzegorz Jaszczyk 14*a2847172SGrzegorz Jaszczyk enum mss_pm_ctrl_handshake { 15*a2847172SGrzegorz Jaszczyk MSS_UN_INITIALIZED = 0, 16*a2847172SGrzegorz Jaszczyk MSS_COMPATIBILITY_ERROR = 1, 17*a2847172SGrzegorz Jaszczyk MSS_ACKNOWLEDGMENT = 2, 18*a2847172SGrzegorz Jaszczyk HOST_ACKNOWLEDGMENT = 3 19*a2847172SGrzegorz Jaszczyk }; 20*a2847172SGrzegorz Jaszczyk 21*a2847172SGrzegorz Jaszczyk enum mss_pm_ctrl_rtos_env { 22*a2847172SGrzegorz Jaszczyk MSS_MULTI_PROCESS_ENV = 0, 23*a2847172SGrzegorz Jaszczyk MSS_SINGLE_PROCESS_ENV = 1, 24*a2847172SGrzegorz Jaszczyk MSS_MAX_PROCESS_ENV 25*a2847172SGrzegorz Jaszczyk }; 26*a2847172SGrzegorz Jaszczyk 27*a2847172SGrzegorz Jaszczyk struct mss_pm_ctrl_block { 28*a2847172SGrzegorz Jaszczyk /* This field is used to synchronize the Host 29*a2847172SGrzegorz Jaszczyk * and MSS initialization sequence 30*a2847172SGrzegorz Jaszczyk * Valid Values 31*a2847172SGrzegorz Jaszczyk * 0 - Un-Initialized 32*a2847172SGrzegorz Jaszczyk * 1 - Compatibility Error 33*a2847172SGrzegorz Jaszczyk * 2 - MSS Acknowledgment 34*a2847172SGrzegorz Jaszczyk * 3 - Host Acknowledgment 35*a2847172SGrzegorz Jaszczyk */ 36*a2847172SGrzegorz Jaszczyk unsigned int handshake; 37*a2847172SGrzegorz Jaszczyk 38*a2847172SGrzegorz Jaszczyk /* 39*a2847172SGrzegorz Jaszczyk * This field include Host IPC version. Once received by the MSS 40*a2847172SGrzegorz Jaszczyk * It will be compared to MSS IPC version and set MSS Acknowledge to 41*a2847172SGrzegorz Jaszczyk * "compatibility error" in case there is no match 42*a2847172SGrzegorz Jaszczyk */ 43*a2847172SGrzegorz Jaszczyk unsigned int ipc_version; 44*a2847172SGrzegorz Jaszczyk unsigned int ipc_base_address; 45*a2847172SGrzegorz Jaszczyk unsigned int ipc_state; 46*a2847172SGrzegorz Jaszczyk 47*a2847172SGrzegorz Jaszczyk /* Following fields defines firmware core architecture */ 48*a2847172SGrzegorz Jaszczyk unsigned int num_of_cores; 49*a2847172SGrzegorz Jaszczyk unsigned int num_of_clusters; 50*a2847172SGrzegorz Jaszczyk unsigned int num_of_cores_per_cluster; 51*a2847172SGrzegorz Jaszczyk 52*a2847172SGrzegorz Jaszczyk /* Following fields define pm trace debug base address */ 53*a2847172SGrzegorz Jaszczyk unsigned int pm_trace_ctrl_base_address; 54*a2847172SGrzegorz Jaszczyk unsigned int pm_trace_info_base_address; 55*a2847172SGrzegorz Jaszczyk unsigned int pm_trace_info_core_size; 56*a2847172SGrzegorz Jaszczyk 57*a2847172SGrzegorz Jaszczyk unsigned int ctrl_blk_size; 58*a2847172SGrzegorz Jaszczyk }; 59*a2847172SGrzegorz Jaszczyk 60*a2847172SGrzegorz Jaszczyk #endif /* MSS_MEM_H */ 61