1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <platform_def.h> 9 10 #include <common/debug.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gicv3.h> 13 #include <plat/common/platform.h> 14 15 #include <marvell_def.h> 16 #include <plat_marvell.h> 17 18 /****************************************************************************** 19 * The following functions are defined as weak to allow a platform to override 20 * the way the GICv3 driver is initialised and used. 21 ****************************************************************************** 22 */ 23 #pragma weak plat_marvell_gic_driver_init 24 #pragma weak plat_marvell_gic_init 25 #pragma weak plat_marvell_gic_cpuif_enable 26 #pragma weak plat_marvell_gic_cpuif_disable 27 #pragma weak plat_marvell_gic_pcpu_init 28 29 /* The GICv3 driver only needs to be initialized in EL3 */ 30 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 31 32 static const interrupt_prop_t marvell_interrupt_props[] = { 33 PLAT_MARVELL_G1S_IRQ_PROPS(INTR_GROUP1S), 34 PLAT_MARVELL_G0_IRQ_PROPS(INTR_GROUP0) 35 }; 36 37 /* 38 * We save and restore the GICv3 context on system suspend. Allocate the 39 * data in the designated EL3 Secure carve-out memory 40 */ 41 static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram"); 42 static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram"); 43 44 /* 45 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 46 * to core position. 47 * 48 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 49 * values read from GICR_TYPER don't have an MT field. To reuse the same 50 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 51 * that read from GICR_TYPER. 52 * 53 * Assumptions: 54 * 55 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 56 * - No CPUs implemented in the system use affinity level 3. 57 */ 58 static unsigned int marvell_gicv3_mpidr_hash(u_register_t mpidr) 59 { 60 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 61 return plat_marvell_calc_core_pos(mpidr); 62 } 63 64 const gicv3_driver_data_t marvell_gic_data = { 65 .gicd_base = PLAT_MARVELL_GICD_BASE, 66 .gicr_base = PLAT_MARVELL_GICR_BASE, 67 .interrupt_props = marvell_interrupt_props, 68 .interrupt_props_num = ARRAY_SIZE(marvell_interrupt_props), 69 .rdistif_num = PLATFORM_CORE_COUNT, 70 .rdistif_base_addrs = rdistif_base_addrs, 71 .mpidr_to_core_pos = marvell_gicv3_mpidr_hash 72 }; 73 74 void plat_marvell_gic_driver_init(void) 75 { 76 /* 77 * The GICv3 driver is initialized in EL3 and does not need 78 * to be initialized again in SEL1. This is because the S-EL1 79 * can use GIC system registers to manage interrupts and does 80 * not need GIC interface base addresses to be configured. 81 */ 82 #if IMAGE_BL31 83 gicv3_driver_init(&marvell_gic_data); 84 #endif 85 } 86 87 /****************************************************************************** 88 * Marvell common helper to initialize the GIC. Only invoked by BL31 89 ****************************************************************************** 90 */ 91 void plat_marvell_gic_init(void) 92 { 93 /* Initialize GIC-600 Multi Chip feature, 94 * only if the maximum number of north bridges 95 * is more than 1 - otherwise no need for multi 96 * chip feature initialization 97 */ 98 #if (PLAT_MARVELL_NORTHB_COUNT > 1) 99 if (gic600_multi_chip_init()) 100 ERROR("GIC-600 Multi Chip initialization failed\n"); 101 #endif 102 gicv3_distif_init(); 103 gicv3_rdistif_init(plat_my_core_pos()); 104 gicv3_cpuif_enable(plat_my_core_pos()); 105 } 106 107 /****************************************************************************** 108 * Marvell common helper to enable the GIC CPU interface 109 ****************************************************************************** 110 */ 111 void plat_marvell_gic_cpuif_enable(void) 112 { 113 gicv3_cpuif_enable(plat_my_core_pos()); 114 } 115 116 /****************************************************************************** 117 * Marvell common helper to disable the GIC CPU interface 118 ****************************************************************************** 119 */ 120 void plat_marvell_gic_cpuif_disable(void) 121 { 122 gicv3_cpuif_disable(plat_my_core_pos()); 123 } 124 125 /****************************************************************************** 126 * Marvell common helper to init. the per-cpu redistributor interface in GICv3 127 ****************************************************************************** 128 */ 129 void plat_marvell_gic_pcpu_init(void) 130 { 131 gicv3_rdistif_init(plat_my_core_pos()); 132 } 133 134 /****************************************************************************** 135 * Marvell common helper to save SPI irq states in GICv3 136 ****************************************************************************** 137 */ 138 void plat_marvell_gic_irq_save(void) 139 { 140 141 /* 142 * If an ITS is available, save its context before 143 * the Redistributor using: 144 * gicv3_its_save_disable(gits_base, &its_ctx[i]) 145 * Additionally, an implementation-defined sequence may 146 * be required to save the whole ITS state. 147 */ 148 149 /* 150 * Save the GIC Redistributors and ITS contexts before the 151 * Distributor context. As we only handle SYSTEM SUSPEND API, 152 * we only need to save the context of the CPU that is issuing 153 * the SYSTEM SUSPEND call, i.e. the current CPU. 154 */ 155 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); 156 157 /* Save the GIC Distributor context */ 158 gicv3_distif_save(&dist_ctx); 159 160 /* 161 * From here, all the components of the GIC can be safely powered down 162 * as long as there is an alternate way to handle wakeup interrupt 163 * sources. 164 */ 165 } 166 167 /****************************************************************************** 168 * Marvell common helper to restore SPI irq states in GICv3 169 ****************************************************************************** 170 */ 171 void plat_marvell_gic_irq_restore(void) 172 { 173 /* Restore the GIC Distributor context */ 174 gicv3_distif_init_restore(&dist_ctx); 175 176 /* 177 * Restore the GIC Redistributor and ITS contexts after the 178 * Distributor context. As we only handle SYSTEM SUSPEND API, 179 * we only need to restore the context of the CPU that issued 180 * the SYSTEM SUSPEND call. 181 */ 182 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); 183 184 /* 185 * If an ITS is available, restore its context after 186 * the Redistributor using: 187 * gicv3_its_restore(gits_base, &its_ctx[i]) 188 * An implementation-defined sequence may be required to 189 * restore the whole ITS state. The ITS must also be 190 * re-enabled after this sequence has been executed. 191 */ 192 } 193 194 /****************************************************************************** 195 * Marvell common helper to save per-cpu PPI irq states in GICv3 196 ****************************************************************************** 197 */ 198 void plat_marvell_gic_irq_pcpu_save(void) 199 { 200 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); 201 } 202 203 /****************************************************************************** 204 * Marvell common helper to restore per-cpu PPI irq states in GICv3 205 ****************************************************************************** 206 */ 207 void plat_marvell_gic_irq_pcpu_restore(void) 208 { 209 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); 210 } 211