1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <assert.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/console.h> 18 #include <lib/utils.h> 19 20 #include <marvell_def.h> 21 #include <plat_marvell.h> 22 23 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 24 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 25 26 /* Weak definitions may be overridden in specific MARVELL standard platform */ 27 #pragma weak bl2_early_platform_setup2 28 #pragma weak bl2_platform_setup 29 #pragma weak bl2_plat_arch_setup 30 #pragma weak bl2_plat_sec_mem_layout 31 32 meminfo_t *bl2_plat_sec_mem_layout(void) 33 { 34 return &bl2_tzram_layout; 35 } 36 37 /***************************************************************************** 38 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 39 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 40 * Copy it to a safe location before its reclaimed by later BL2 functionality. 41 ***************************************************************************** 42 */ 43 void marvell_bl2_early_platform_setup(meminfo_t *mem_layout) 44 { 45 /* Initialize the console to provide early debug support */ 46 marvell_console_boot_init(); 47 48 /* Setup the BL2 memory layout */ 49 bl2_tzram_layout = *mem_layout; 50 51 /* Initialise the IO layer and register platform IO devices */ 52 plat_marvell_io_setup(); 53 } 54 55 56 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, 57 u_register_t arg2, u_register_t arg3) 58 { 59 struct meminfo *mem_layout = (struct meminfo *)arg1; 60 61 marvell_bl2_early_platform_setup(mem_layout); 62 } 63 64 void bl2_platform_setup(void) 65 { 66 /* Nothing to do */ 67 } 68 69 /***************************************************************************** 70 * Perform the very early platform specific architectural setup here. At the 71 * moment this is only initializes the mmu in a quick and dirty way. 72 ***************************************************************************** 73 */ 74 void marvell_bl2_plat_arch_setup(void) 75 { 76 marvell_setup_page_tables(bl2_tzram_layout.total_base, 77 bl2_tzram_layout.total_size, 78 BL_CODE_BASE, 79 BL_CODE_END, 80 BL_RO_DATA_BASE, 81 BL_RO_DATA_END 82 #if USE_COHERENT_MEM 83 , BL_COHERENT_RAM_BASE, 84 BL_COHERENT_RAM_END 85 #endif 86 ); 87 enable_mmu_el1(0); 88 } 89 90 void bl2_plat_arch_setup(void) 91 { 92 marvell_bl2_plat_arch_setup(); 93 } 94 95 int marvell_bl2_handle_post_image_load(unsigned int image_id) 96 { 97 int err = 0; 98 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 99 100 assert(bl_mem_params); 101 102 switch (image_id) { 103 104 case BL33_IMAGE_ID: 105 /* BL33 expects to receive the primary CPU MPID (through r0) */ 106 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 107 bl_mem_params->ep_info.spsr = marvell_get_spsr_for_bl33_entry(); 108 break; 109 #ifdef SCP_BL2_BASE 110 case SCP_BL2_IMAGE_ID: 111 /* The subsequent handling of SCP_BL2 is platform specific */ 112 err = bl2_plat_handle_scp_bl2(&bl_mem_params->image_info); 113 if (err) { 114 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 115 } 116 break; 117 #endif 118 default: 119 /* Do nothing in default case */ 120 break; 121 } 122 123 return err; 124 125 } 126 127 /******************************************************************************* 128 * This function can be used by the platforms to update/use image 129 * information for given `image_id`. 130 ******************************************************************************/ 131 int bl2_plat_handle_post_image_load(unsigned int image_id) 132 { 133 return marvell_bl2_handle_post_image_load(image_id); 134 } 135 136