1*b5a06637SKonstantin Porotchkin /* 2*b5a06637SKonstantin Porotchkin * Copyright (C) 2021 Marvell International Ltd. 3*b5a06637SKonstantin Porotchkin * 4*b5a06637SKonstantin Porotchkin * SPDX-License-Identifier: BSD-3-Clause 5*b5a06637SKonstantin Porotchkin * https://spdx.org/licenses 6*b5a06637SKonstantin Porotchkin */ 7*b5a06637SKonstantin Porotchkin 8*b5a06637SKonstantin Porotchkin #ifndef MSS_DEFS_H 9*b5a06637SKonstantin Porotchkin #define MSS_DEFS_H 10*b5a06637SKonstantin Porotchkin 11*b5a06637SKonstantin Porotchkin #define MSS_DMA_SRCBR(base) (base + 0xC0) 12*b5a06637SKonstantin Porotchkin #define MSS_DMA_DSTBR(base) (base + 0xC4) 13*b5a06637SKonstantin Porotchkin #define MSS_DMA_CTRLR(base) (base + 0xC8) 14*b5a06637SKonstantin Porotchkin #define MSS_M3_RSTCR(base) (base + 0xFC) 15*b5a06637SKonstantin Porotchkin 16*b5a06637SKonstantin Porotchkin #define MSS_DMA_CTRLR_SIZE_OFFSET (0) 17*b5a06637SKonstantin Porotchkin #define MSS_DMA_CTRLR_REQ_OFFSET (15) 18*b5a06637SKonstantin Porotchkin #define MSS_DMA_CTRLR_REQ_SET (1) 19*b5a06637SKonstantin Porotchkin #define MSS_DMA_CTRLR_ACK_OFFSET (12) 20*b5a06637SKonstantin Porotchkin #define MSS_DMA_CTRLR_ACK_MASK (0x1) 21*b5a06637SKonstantin Porotchkin #define MSS_DMA_CTRLR_ACK_READY (1) 22*b5a06637SKonstantin Porotchkin #define MSS_M3_RSTCR_RST_OFFSET (0) 23*b5a06637SKonstantin Porotchkin #define MSS_M3_RSTCR_RST_OFF (1) 24*b5a06637SKonstantin Porotchkin 25*b5a06637SKonstantin Porotchkin #define MSS_FW_READY_MAGIC 0x46575144 /* FWRD */ 26*b5a06637SKonstantin Porotchkin 27*b5a06637SKonstantin Porotchkin #define MSS_AP_REGS_OFFSET 0x00580000 28*b5a06637SKonstantin Porotchkin #define MSS_CP_SRAM_OFFSET 0x00220000 29*b5a06637SKonstantin Porotchkin #define MSS_CP_REGS_OFFSET 0x00280000 30*b5a06637SKonstantin Porotchkin 31*b5a06637SKonstantin Porotchkin void mss_start_cp_cm3(int cp); 32*b5a06637SKonstantin Porotchkin 33*b5a06637SKonstantin Porotchkin #endif /* MSS_DEFS_H */ 34