1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <armada_common.h> 9 10 /* 11 * If bootrom is currently at BLE there's no need to include the memory 12 * maps structure at this point 13 */ 14 #include <mvebu_def.h> 15 #ifndef IMAGE_BLE 16 17 /***************************************************************************** 18 * AMB Configuration 19 ***************************************************************************** 20 */ 21 struct addr_map_win amb_memory_map[] = { 22 /* CP1 SPI1 CS0 Direct Mode access */ 23 {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, 24 }; 25 26 int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, 27 uintptr_t base) 28 { 29 *win = amb_memory_map; 30 if (*win == NULL) 31 *size = 0; 32 else 33 *size = ARRAY_SIZE(amb_memory_map); 34 35 return 0; 36 } 37 #endif 38 39 /***************************************************************************** 40 * IO WIN Configuration 41 ***************************************************************************** 42 */ 43 struct addr_map_win io_win_memory_map[] = { 44 /* CP1 (MCI0) internal regs */ 45 {0x00000000f4000000, 0x2000000, MCI_0_TID}, 46 #ifndef IMAGE_BLE 47 /* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/ 48 {0x00000000f9000000, 0x2000000, MCI_0_TID}, 49 /* PCIe1 on CP1*/ 50 {0x00000000fb000000, 0x1000000, MCI_0_TID}, 51 /* PCIe2 on CP1*/ 52 {0x00000000fc000000, 0x1000000, MCI_0_TID}, 53 /* MCI 0 indirect window */ 54 {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, 55 /* MCI 1 indirect window */ 56 {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, 57 #endif 58 }; 59 60 uint32_t marvell_get_io_win_gcr_target(int ap_index) 61 { 62 return PIDI_TID; 63 } 64 65 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, 66 uint32_t *size) 67 { 68 *win = io_win_memory_map; 69 if (*win == NULL) 70 *size = 0; 71 else 72 *size = ARRAY_SIZE(io_win_memory_map); 73 74 return 0; 75 } 76 77 #ifndef IMAGE_BLE 78 /***************************************************************************** 79 * IOB Configuration 80 ***************************************************************************** 81 */ 82 struct addr_map_win iob_memory_map_cp0[] = { 83 /* CP0 */ 84 /* PEX1_X1 window */ 85 {0x00000000f7000000, 0x1000000, PEX1_TID}, 86 /* PEX2_X1 window */ 87 {0x00000000f8000000, 0x1000000, PEX2_TID}, 88 /* PEX0_X4 window */ 89 {0x00000000f6000000, 0x1000000, PEX0_TID}, 90 {0x00000000c0000000, 0x30000000, PEX0_TID}, 91 {0x0000000800000000, 0x100000000, PEX0_TID}, 92 }; 93 94 struct addr_map_win iob_memory_map_cp1[] = { 95 /* CP1 */ 96 /* SPI1_CS0 (RUNIT) window */ 97 {0x00000000f9000000, 0x1000000, RUNIT_TID}, 98 /* PEX1_X1 window */ 99 {0x00000000fb000000, 0x1000000, PEX1_TID}, 100 /* PEX2_X1 window */ 101 {0x00000000fc000000, 0x1000000, PEX2_TID}, 102 /* PEX0_X4 window */ 103 {0x00000000fa000000, 0x1000000, PEX0_TID} 104 }; 105 106 int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, 107 uintptr_t base) 108 { 109 switch (base) { 110 case MVEBU_CP_REGS_BASE(0): 111 *win = iob_memory_map_cp0; 112 *size = ARRAY_SIZE(iob_memory_map_cp0); 113 return 0; 114 case MVEBU_CP_REGS_BASE(1): 115 *win = iob_memory_map_cp1; 116 *size = ARRAY_SIZE(iob_memory_map_cp1); 117 return 0; 118 default: 119 *size = 0; 120 *win = 0; 121 return 1; 122 } 123 } 124 #endif 125 126 /***************************************************************************** 127 * CCU Configuration 128 ***************************************************************************** 129 */ 130 struct addr_map_win ccu_memory_map[] = { 131 #ifdef IMAGE_BLE 132 {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ 133 #else 134 #if LLC_SRAM 135 /* This entry is prepared for OP-TEE OS that enables the LLC SRAM 136 * and changes the window target to SRAM_TID. 137 */ 138 {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, 139 #endif 140 {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ 141 {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ 142 {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */ 143 #endif 144 }; 145 146 uint32_t marvell_get_ccu_gcr_target(int ap) 147 { 148 return DRAM_0_TID; 149 } 150 151 int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, 152 uint32_t *size) 153 { 154 *win = ccu_memory_map; 155 *size = ARRAY_SIZE(ccu_memory_map); 156 157 return 0; 158 } 159 160 #ifndef IMAGE_BLE 161 /***************************************************************************** 162 * SoC PM configuration 163 ***************************************************************************** 164 */ 165 /* CP GPIO should be used and the GPIOs should be within same GPIO register */ 166 struct power_off_method pm_cfg = { 167 .type = PMIC_GPIO, 168 .cfg.gpio.pin_count = 1, 169 .cfg.gpio.info = {{0, 35} }, 170 .cfg.gpio.step_count = 7, 171 .cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1}, 172 .cfg.gpio.delay_ms = 10, 173 }; 174 175 void *plat_marvell_get_pm_cfg(void) 176 { 177 /* Return the PM configurations */ 178 return &pm_cfg; 179 } 180 181 /* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */ 182 #else 183 /***************************************************************************** 184 * SKIP IMAGE Configuration 185 ***************************************************************************** 186 */ 187 #if PLAT_RECOVERY_IMAGE_ENABLE 188 struct skip_image skip_im = { 189 .detection_method = GPIO, 190 .info.gpio.num = 33, 191 .info.gpio.button_state = HIGH, 192 .info.test.cp_ap = CP, 193 .info.test.cp_index = 0, 194 }; 195 196 void *plat_marvell_get_skip_image_data(void) 197 { 198 /* Return the skip_image configurations */ 199 return &skip_im; 200 } 201 #endif 202 #endif 203