1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <arch_helpers.h> 9 #include <common/debug.h> 10 #include <drivers/mentor/mi2cv.h> 11 #include <lib/mmio.h> 12 13 #include <mv_ddr_if.h> 14 #include <mvebu_def.h> 15 #include <plat_marvell.h> 16 17 #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0) 18 #define MVEBU_AP_MPP_CTRL4_OFFS 16 19 #define MVEBU_AP_MPP_CTRL5_OFFS 20 20 #define MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA 0x3 21 #define MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA 0x3 22 23 #define MVEBU_CP_MPP_CTRL37_OFFS 20 24 #define MVEBU_CP_MPP_CTRL38_OFFS 24 25 #define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2 26 #define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2 27 28 #define MVEBU_MPP_CTRL_MASK 0xf 29 30 /* 31 * This struct provides the DRAM training code with 32 * the appropriate board DRAM configuration 33 */ 34 static struct mv_ddr_topology_map board_topology_map = { 35 /* MISL board with 1CS 8Gb x4 devices of Micron 2400T */ 36 DEBUG_LEVEL_ERROR, 37 0x1, /* active interfaces */ 38 /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ 39 { { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */ 40 {0x1, 0x0, 0, 0}, 41 {0x1, 0x0, 0, 0}, 42 {0x1, 0x0, 0, 0}, 43 {0x1, 0x0, 0, 0}, 44 {0x1, 0x0, 0, 0}, 45 {0x1, 0x0, 0, 0}, 46 {0x1, 0x0, 0, 0}, 47 {0x1, 0x0, 0, 0} }, 48 /* TODO: double check if the speed bin is 2400T */ 49 SPEED_BIN_DDR_2400T, /* speed_bin */ 50 MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ 51 MV_DDR_DIE_CAP_8GBIT, /* die capacity */ 52 MV_DDR_FREQ_SAR, /* frequency */ 53 0, 0, /* cas_l, cas_wl */ 54 MV_DDR_TEMP_LOW} }, /* temperature */ 55 #if DDR32 56 MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ 57 #else 58 MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ 59 #endif 60 MV_DDR_CFG_SPD, /* ddr configuration data source */ 61 NOT_COMBINED, /* ddr twin-die combined*/ 62 { {0} }, /* raw spd data */ 63 {0}, /* timing parameters */ 64 { /* electrical configuration */ 65 { /* memory electrical configuration */ 66 MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ 67 { 68 MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ 69 MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ 70 }, 71 { 72 MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ 73 MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */ 74 }, 75 MV_DDR_DIC_RZQ_DIV7 /* dic */ 76 }, 77 { /* phy electrical configuration */ 78 MV_DDR_OHM_30, /* data_drv_p */ 79 MV_DDR_OHM_30, /* data_drv_n */ 80 MV_DDR_OHM_30, /* ctrl_drv_p */ 81 MV_DDR_OHM_30, /* ctrl_drv_n */ 82 { 83 MV_DDR_OHM_60, /* odt_p 1cs */ 84 MV_DDR_OHM_120 /* odt_p 2cs */ 85 }, 86 { 87 MV_DDR_OHM_60, /* odt_n 1cs */ 88 MV_DDR_OHM_120 /* odt_n 2cs */ 89 }, 90 }, 91 { /* mac electrical configuration */ 92 MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ 93 MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ 94 MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ 95 }, 96 } 97 }; 98 99 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 100 { 101 /* Return the board topology as defined in the board code */ 102 return &board_topology_map; 103 } 104 105 static void mpp_config(void) 106 { 107 uintptr_t reg; 108 uint32_t val; 109 110 reg = MVEBU_CP_MPP_REGS(0, 4); 111 /* configure CP0 MPP 37 and 38 to i2c */ 112 val = mmio_read_32(reg); 113 val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) | 114 (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS)); 115 val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA << 116 MVEBU_CP_MPP_CTRL37_OFFS) | 117 (MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA << 118 MVEBU_CP_MPP_CTRL38_OFFS); 119 mmio_write_32(reg, val); 120 } 121 122 /* 123 * This function may modify the default DRAM parameters 124 * based on information received from SPD or bootloader 125 * configuration located on non volatile storage 126 */ 127 void plat_marvell_dram_update_topology(void) 128 { 129 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); 130 131 INFO("Gathering DRAM information\n"); 132 133 if (tm->cfg_src == MV_DDR_CFG_SPD) { 134 /* configure MPPs to enable i2c */ 135 mpp_config(); 136 137 /* initialize i2c */ 138 i2c_init((void *)MVEBU_CP0_I2C_BASE); 139 140 /* select SPD memory page 0 to access DRAM configuration */ 141 i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0); 142 143 /* read data from spd */ 144 i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes, 145 sizeof(tm->spd_data.all_bytes)); 146 } 147 } 148