1*b5c850d4SMarcin Wojtas /* 2*b5c850d4SMarcin Wojtas * Copyright (C) 2018 Marvell International Ltd. 3*b5c850d4SMarcin Wojtas * 4*b5c850d4SMarcin Wojtas * SPDX-License-Identifier: BSD-3-Clause 5*b5c850d4SMarcin Wojtas * https://spdx.org/licenses 6*b5c850d4SMarcin Wojtas */ 7*b5c850d4SMarcin Wojtas 8*b5c850d4SMarcin Wojtas #ifndef IO_ADDR_DEC_H 9*b5c850d4SMarcin Wojtas #define IO_ADDR_DEC_H 10*b5c850d4SMarcin Wojtas 11*b5c850d4SMarcin Wojtas #include <stdint.h> 12*b5c850d4SMarcin Wojtas 13*b5c850d4SMarcin Wojtas /* There are 5 configurable cpu decoder windows. */ 14*b5c850d4SMarcin Wojtas #define DRAM_WIN_MAP_NUM_MAX 5 15*b5c850d4SMarcin Wojtas /* Target number for dram in cpu decoder windows. */ 16*b5c850d4SMarcin Wojtas #define DRAM_CPU_DEC_TARGET_NUM 0 17*b5c850d4SMarcin Wojtas 18*b5c850d4SMarcin Wojtas /* 19*b5c850d4SMarcin Wojtas * Not all configurable decode windows could be used for dram, some units have 20*b5c850d4SMarcin Wojtas * to reserve one decode window for other unit they have to communicate with; 21*b5c850d4SMarcin Wojtas * for example, DMA engineer has 3 configurable windows, but only two could be 22*b5c850d4SMarcin Wojtas * for dram while the last one has to be for pcie, so for DMA, its max_dram_win 23*b5c850d4SMarcin Wojtas * is 2. 24*b5c850d4SMarcin Wojtas */ 25*b5c850d4SMarcin Wojtas struct dec_win_config { 26*b5c850d4SMarcin Wojtas uint32_t dec_reg_base; /* IO address decoder register base address */ 27*b5c850d4SMarcin Wojtas uint32_t win_attr; /* IO address decoder windows attributes */ 28*b5c850d4SMarcin Wojtas /* How many configurable dram decoder windows that this unit has; */ 29*b5c850d4SMarcin Wojtas uint32_t max_dram_win; 30*b5c850d4SMarcin Wojtas /* The decoder windows number including remapping that this unit has */ 31*b5c850d4SMarcin Wojtas uint32_t max_remap; 32*b5c850d4SMarcin Wojtas /* The offset between continuous decode windows 33*b5c850d4SMarcin Wojtas * within the same unit, typically 0x10 34*b5c850d4SMarcin Wojtas */ 35*b5c850d4SMarcin Wojtas uint32_t win_offset; 36*b5c850d4SMarcin Wojtas }; 37*b5c850d4SMarcin Wojtas 38*b5c850d4SMarcin Wojtas struct dram_win { 39*b5c850d4SMarcin Wojtas uintptr_t base_addr; 40*b5c850d4SMarcin Wojtas uintptr_t win_size; 41*b5c850d4SMarcin Wojtas }; 42*b5c850d4SMarcin Wojtas 43*b5c850d4SMarcin Wojtas struct dram_win_map { 44*b5c850d4SMarcin Wojtas int dram_win_num; 45*b5c850d4SMarcin Wojtas struct dram_win dram_windows[DRAM_WIN_MAP_NUM_MAX]; 46*b5c850d4SMarcin Wojtas }; 47*b5c850d4SMarcin Wojtas 48*b5c850d4SMarcin Wojtas /* 49*b5c850d4SMarcin Wojtas * init_io_addr_dec 50*b5c850d4SMarcin Wojtas * 51*b5c850d4SMarcin Wojtas * This function initializes io address decoder windows by 52*b5c850d4SMarcin Wojtas * cpu dram window mapping information 53*b5c850d4SMarcin Wojtas * 54*b5c850d4SMarcin Wojtas * @input: N/A 55*b5c850d4SMarcin Wojtas * - dram_wins_map: cpu dram windows mapping 56*b5c850d4SMarcin Wojtas * - io_dec_config: io address decoder windows configuration 57*b5c850d4SMarcin Wojtas * - io_unit_num: io address decoder unit number 58*b5c850d4SMarcin Wojtas * @output: N/A 59*b5c850d4SMarcin Wojtas * 60*b5c850d4SMarcin Wojtas * @return: 0 on success and others on failure 61*b5c850d4SMarcin Wojtas */ 62*b5c850d4SMarcin Wojtas int init_io_addr_dec(struct dram_win_map *dram_wins_map, 63*b5c850d4SMarcin Wojtas struct dec_win_config *io_dec_config, 64*b5c850d4SMarcin Wojtas uint32_t io_unit_num); 65*b5c850d4SMarcin Wojtas 66*b5c850d4SMarcin Wojtas #endif /* IO_ADDR_DEC_H */ 67