1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef A3700_PLAT_DEF_H 9 #define A3700_PLAT_DEF_H 10 11 #include <marvell_def.h> 12 13 14 #define MVEBU_MAX_CPUS_PER_CLUSTER 2 15 16 #define MVEBU_PRIMARY_CPU 0x0 17 18 /* 19 * The counter on A3700 is always fed from reference 25M clock (XTAL). 20 * However minimal CPU counter prescaler is 2, so the counter 21 * frequency will be divided by 2, the number is 12.5M 22 */ 23 #define COUNTER_FREQUENCY 12500000 24 25 #define MVEBU_REGS_BASE 0xD0000000 26 27 /***************************************************************************** 28 * MVEBU memory map related constants 29 ***************************************************************************** 30 */ 31 /* Aggregate of all devices in the first GB */ 32 #define DEVICE0_BASE MVEBU_REGS_BASE 33 #define DEVICE0_SIZE 0x10000000 34 35 /***************************************************************************** 36 * GIC-500 & interrupt handling related constants 37 ***************************************************************************** 38 */ 39 /* Base MVEBU compatible GIC memory map */ 40 #define MVEBU_GICD_BASE 0x1D00000 41 #define MVEBU_GICR_BASE 0x1D40000 42 #define MVEBU_GICC_BASE 0x1D80000 43 44 /* CCI-400 */ 45 #define MVEBU_CCI_BASE 0x8000000 46 47 /***************************************************************************** 48 * North and south bridge register base 49 ***************************************************************************** 50 */ 51 #define MVEBU_NB_REGS_BASE (MVEBU_REGS_BASE + 0x13000) 52 #define MVEBU_SB_REGS_BASE (MVEBU_REGS_BASE + 0x18000) 53 54 /***************************************************************************** 55 * GPIO registers related constants 56 ***************************************************************************** 57 */ 58 /* North and south bridge GPIO register base address */ 59 #define MVEBU_NB_GPIO_REG_BASE (MVEBU_NB_REGS_BASE + 0x800) 60 #define MVEBU_NB_GPIO_IRQ_REG_BASE (MVEBU_NB_REGS_BASE + 0xC00) 61 #define MVEBU_SB_GPIO_REG_BASE (MVEBU_SB_REGS_BASE + 0x800) 62 #define MVEBU_SB_GPIO_IRQ_REG_BASE (MVEBU_SB_REGS_BASE + 0xC00) 63 #define MVEBU_NB_SB_IRQ_REG_BASE (MVEBU_REGS_BASE + 0x8A00) 64 65 /* North Bridge GPIO selection register */ 66 #define MVEBU_NB_GPIO_SEL_REG (MVEBU_NB_GPIO_REG_BASE + 0x30) 67 #define MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG (MVEBU_NB_GPIO_REG_BASE + 0x04) 68 /* I2C1 GPIO Enable bit offset */ 69 #define MVEBU_GPIO_TW1_GPIO_EN_OFF (10) 70 /* SPI pins mode bit offset */ 71 #define MVEBU_GPIO_NB_SPI_PIN_MODE_OFF (28) 72 73 /***************************************************************************** 74 * DRAM registers related constants 75 ***************************************************************************** 76 */ 77 #define MVEBU_DRAM_REG_BASE (MVEBU_REGS_BASE) 78 79 /***************************************************************************** 80 * SB wake-up registers related constants 81 ***************************************************************************** 82 */ 83 #define MVEBU_SB_WAKEUP_REG_BASE (MVEBU_REGS_BASE + 0x19000) 84 85 /***************************************************************************** 86 * PMSU registers related constants 87 ***************************************************************************** 88 */ 89 #define MVEBU_PMSU_REG_BASE (MVEBU_REGS_BASE + 0x14000) 90 91 /***************************************************************************** 92 * North Bridge Step-Down Registers 93 ***************************************************************************** 94 */ 95 #define MVEBU_NB_STEP_DOWN_REG_BASE (MVEBU_REGS_BASE + 0x12800) 96 97 /***************************************************************************** 98 * DRAM CS memory map register base 99 ***************************************************************************** 100 */ 101 #define MVEBU_CS_MMAP_REG_BASE (MVEBU_REGS_BASE + 0x200) 102 103 /***************************************************************************** 104 * CPU decoder window registers related constants 105 ***************************************************************************** 106 */ 107 #define MVEBU_CPU_DEC_WIN_REG_BASE (MVEBU_REGS_BASE + 0xCF00) 108 109 /***************************************************************************** 110 * AVS registers related constants 111 ***************************************************************************** 112 */ 113 #define MVEBU_AVS_REG_BASE (MVEBU_REGS_BASE + 0x11500) 114 115 116 /***************************************************************************** 117 * AVS registers related constants 118 ***************************************************************************** 119 */ 120 #define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300) 121 122 #endif /* A3700_PLAT_DEF_H */ 123