1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <string.h> 9 10 #include <lib/mmio.h> 11 12 #include <dram_win.h> 13 #include <marvell_plat_priv.h> 14 #include <mvebu.h> 15 #include <plat_marvell.h> 16 17 /* Armada 3700 has 5 configurable windows */ 18 #define MV_CPU_WIN_NUM 5 19 20 #define CPU_WIN_DISABLED 0 21 #define CPU_WIN_ENABLED 1 22 23 /* 24 * There are 2 different cpu decode window configuration cases: 25 * - DRAM size is not over 2GB; 26 * - DRAM size is 4GB. 27 */ 28 enum cpu_win_config_num { 29 CPU_WIN_CONFIG_DRAM_NOT_OVER_2GB = 0, 30 CPU_WIN_CONFIG_DRAM_4GB, 31 CPU_WIN_CONFIG_MAX 32 }; 33 34 enum cpu_win_target { 35 CPU_WIN_TARGET_DRAM = 0, 36 CPU_WIN_TARGET_INTERNAL_REG, 37 CPU_WIN_TARGET_PCIE, 38 CPU_WIN_TARGET_PCIE_OVER_MCI, 39 CPU_WIN_TARGET_BOOT_ROM, 40 CPU_WIN_TARGET_MCI_EXTERNAL, 41 CPU_WIN_TARGET_RWTM_RAM = 7, 42 CPU_WIN_TARGET_CCI400_REG 43 }; 44 45 struct cpu_win_configuration { 46 uint32_t enabled; 47 enum cpu_win_target target; 48 uint64_t base_addr; 49 uint64_t size; 50 uint64_t remap_addr; 51 }; 52 53 struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = { 54 /* 55 * When total dram size is not over 2GB: 56 * DDR window 0 is configured in tim header, its size may be not 512MB, 57 * but the actual dram size, no need to configure it again; 58 * other cpu windows are kept as default. 59 */ 60 { 61 /* enabled 62 * target 63 * base 64 * size 65 * remap 66 */ 67 {CPU_WIN_ENABLED, 68 CPU_WIN_TARGET_DRAM, 69 0x0, 70 0x08000000, 71 0x0}, 72 {CPU_WIN_ENABLED, 73 CPU_WIN_TARGET_MCI_EXTERNAL, 74 0xe0000000, 75 0x08000000, 76 0xe0000000}, 77 {CPU_WIN_ENABLED, 78 CPU_WIN_TARGET_PCIE, 79 0xe8000000, 80 0x08000000, 81 0xe8000000}, 82 {CPU_WIN_ENABLED, 83 CPU_WIN_TARGET_RWTM_RAM, 84 0xf0000000, 85 0x00020000, 86 0x1fff0000}, 87 {CPU_WIN_ENABLED, 88 CPU_WIN_TARGET_PCIE_OVER_MCI, 89 0x80000000, 90 0x10000000, 91 0x80000000}, 92 }, 93 94 /* 95 * If total dram size is more than 2GB, now there is only one case - 4GB 96 * dram; we will use below cpu windows configurations: 97 * - Internal Regs, CCI-400, Boot Rom and PCIe windows are kept as 98 * default; 99 * - Use 4 CPU decode windows for DRAM, which cover 3.375GB DRAM; 100 * DDR window 0 is configured in tim header with 2GB size, no need to 101 * configure it again here; 102 * 103 * 0xFFFFFFFF ---> |-----------------------| 104 * | Boot ROM | 64KB 105 * 0xFFF00000 ---> +-----------------------+ 106 * : : 107 * 0xF0000000 ---> |-----------------------| 108 * | PCIE | 128 MB 109 * 0xE8000000 ---> |-----------------------| 110 * | DDR window 3 | 128 MB 111 * 0xE0000000 ---> +-----------------------+ 112 * : : 113 * 0xD8010000 ---> |-----------------------| 114 * | CCI Regs | 64 KB 115 * 0xD8000000 ---> +-----------------------+ 116 * : : 117 * : : 118 * 0xD2000000 ---> +-----------------------+ 119 * | Internal Regs | 32MB 120 * 0xD0000000 ---> |-----------------------| 121 * | DDR window 2 | 256 MB 122 * 0xC0000000 ---> |-----------------------| 123 * | | 124 * | DDR window 1 | 1 GB 125 * | | 126 * 0x80000000 ---> |-----------------------| 127 * | | 128 * | | 129 * | DDR window 0 | 2 GB 130 * | | 131 * | | 132 * 0x00000000 ---> +-----------------------+ 133 */ 134 { 135 /* win_id 136 * target 137 * base 138 * size 139 * remap 140 */ 141 {CPU_WIN_ENABLED, 142 CPU_WIN_TARGET_DRAM, 143 0x0, 144 0x80000000, 145 0x0}, 146 {CPU_WIN_ENABLED, 147 CPU_WIN_TARGET_DRAM, 148 0x80000000, 149 0x40000000, 150 0x80000000}, 151 {CPU_WIN_ENABLED, 152 CPU_WIN_TARGET_DRAM, 153 0xc0000000, 154 0x10000000, 155 0xc0000000}, 156 {CPU_WIN_ENABLED, 157 CPU_WIN_TARGET_DRAM, 158 0xe0000000, 159 0x08000000, 160 0xe0000000}, 161 {CPU_WIN_ENABLED, 162 CPU_WIN_TARGET_PCIE, 163 0xe8000000, 164 0x08000000, 165 0xe8000000}, 166 }, 167 }; 168 169 /* 170 * dram_win_map_build 171 * 172 * This function builds cpu dram windows mapping 173 * which includes base address and window size by 174 * reading cpu dram decode windows registers. 175 * 176 * @input: N/A 177 * 178 * @output: 179 * - win_map: cpu dram windows mapping 180 * 181 * @return: N/A 182 */ 183 void dram_win_map_build(struct dram_win_map *win_map) 184 { 185 int32_t win_id; 186 struct dram_win *win; 187 uint32_t base_reg, ctrl_reg, size_reg, enabled, target; 188 189 memset(win_map, 0, sizeof(struct dram_win_map)); 190 for (win_id = 0; win_id < DRAM_WIN_MAP_NUM_MAX; win_id++) { 191 ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); 192 target = (ctrl_reg & CPU_DEC_CR_WIN_TARGET_MASK) >> 193 CPU_DEC_CR_WIN_TARGET_OFFS; 194 enabled = ctrl_reg & CPU_DEC_CR_WIN_ENABLE; 195 /* Ignore invalid and non-dram windows*/ 196 if ((enabled == 0) || (target != DRAM_CPU_DEC_TARGET_NUM)) 197 continue; 198 199 win = win_map->dram_windows + win_map->dram_win_num; 200 base_reg = mmio_read_32(CPU_DEC_WIN_BASE_REG(win_id)); 201 size_reg = mmio_read_32(CPU_DEC_WIN_SIZE_REG(win_id)); 202 /* Base reg [15:0] corresponds to transaction address [39:16] */ 203 win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> 204 CPU_DEC_BR_BASE_OFFS; 205 win->base_addr *= CPU_DEC_CR_WIN_SIZE_ALIGNMENT; 206 /* 207 * Size reg [15:0] is programmed from LSB to MSB as a sequence 208 * of 1s followed by a sequence of 0s and the number of 1s 209 * specifies the size of the window in 64 KB granularity, 210 * for example, a value of 00FFh specifies 256 x 64 KB = 16 MB 211 */ 212 win->win_size = (size_reg & CPU_DEC_CR_WIN_SIZE_MASK) >> 213 CPU_DEC_CR_WIN_SIZE_OFFS; 214 win->win_size = (win->win_size + 1) * 215 CPU_DEC_CR_WIN_SIZE_ALIGNMENT; 216 217 win_map->dram_win_num++; 218 } 219 } 220 221 static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg) 222 { 223 uint32_t base_reg, ctrl_reg, size_reg, remap_reg; 224 225 /* Disable window */ 226 ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); 227 ctrl_reg &= ~CPU_DEC_CR_WIN_ENABLE; 228 mmio_write_32(CPU_DEC_WIN_CTRL_REG(win_id), ctrl_reg); 229 230 /* For an disabled window, only disable it. */ 231 if (!win_cfg->enabled) 232 return; 233 234 /* Set Base Register */ 235 base_reg = (uint32_t)(win_cfg->base_addr / 236 CPU_DEC_CR_WIN_SIZE_ALIGNMENT); 237 base_reg <<= CPU_DEC_BR_BASE_OFFS; 238 base_reg &= CPU_DEC_BR_BASE_MASK; 239 mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg); 240 241 /* Set Remap Register with the same value 242 * as the <Base> field in Base Register 243 */ 244 remap_reg = (uint32_t)(win_cfg->remap_addr / 245 CPU_DEC_CR_WIN_SIZE_ALIGNMENT); 246 remap_reg <<= CPU_DEC_RLR_REMAP_LOW_OFFS; 247 remap_reg &= CPU_DEC_RLR_REMAP_LOW_MASK; 248 mmio_write_32(CPU_DEC_REMAP_LOW_REG(win_id), remap_reg); 249 250 /* Set Size Register */ 251 size_reg = (win_cfg->size / CPU_DEC_CR_WIN_SIZE_ALIGNMENT) - 1; 252 size_reg <<= CPU_DEC_CR_WIN_SIZE_OFFS; 253 size_reg &= CPU_DEC_CR_WIN_SIZE_MASK; 254 mmio_write_32(CPU_DEC_WIN_SIZE_REG(win_id), size_reg); 255 256 /* Set Control Register - set target id and enable window */ 257 ctrl_reg &= ~CPU_DEC_CR_WIN_TARGET_MASK; 258 ctrl_reg |= (win_cfg->target << CPU_DEC_CR_WIN_TARGET_OFFS); 259 ctrl_reg |= CPU_DEC_CR_WIN_ENABLE; 260 mmio_write_32(CPU_DEC_WIN_CTRL_REG(win_id), ctrl_reg); 261 } 262 263 void cpu_wins_init(void) 264 { 265 uint32_t cfg_idx, win_id; 266 267 if (mvebu_get_dram_size(MVEBU_REGS_BASE) <= _2GB_) 268 cfg_idx = CPU_WIN_CONFIG_DRAM_NOT_OVER_2GB; 269 else 270 cfg_idx = CPU_WIN_CONFIG_DRAM_4GB; 271 272 /* Window 0 is configured always for DRAM in tim header 273 * already, no need to configure it again here 274 */ 275 for (win_id = 1; win_id < MV_CPU_WIN_NUM; win_id++) 276 cpu_win_set(win_id, &mv_cpu_wins[cfg_idx][win_id]); 277 } 278 279