1*b5c850d4SMarcin Wojtas /*
2*b5c850d4SMarcin Wojtas * Copyright (C) 2018 Marvell International Ltd.
3*b5c850d4SMarcin Wojtas *
4*b5c850d4SMarcin Wojtas * SPDX-License-Identifier: BSD-3-Clause
5*b5c850d4SMarcin Wojtas * https://spdx.org/licenses
6*b5c850d4SMarcin Wojtas */
7*b5c850d4SMarcin Wojtas
8*b5c850d4SMarcin Wojtas #include <lib/mmio.h>
9*b5c850d4SMarcin Wojtas
10*b5c850d4SMarcin Wojtas #include <armada_common.h>
11*b5c850d4SMarcin Wojtas #include <dram_win.h>
12*b5c850d4SMarcin Wojtas #include <io_addr_dec.h>
13*b5c850d4SMarcin Wojtas #include <marvell_plat_priv.h>
14*b5c850d4SMarcin Wojtas #include <plat_marvell.h>
15*b5c850d4SMarcin Wojtas
16*b5c850d4SMarcin Wojtas /* This routine does MPP initialization */
marvell_bl31_mpp_init(void)17*b5c850d4SMarcin Wojtas static void marvell_bl31_mpp_init(void)
18*b5c850d4SMarcin Wojtas {
19*b5c850d4SMarcin Wojtas mmio_clrbits_32(MVEBU_NB_GPIO_SEL_REG, 1 << MVEBU_GPIO_TW1_GPIO_EN_OFF);
20*b5c850d4SMarcin Wojtas
21*b5c850d4SMarcin Wojtas /* Set hidden GPIO setting for SPI.
22*b5c850d4SMarcin Wojtas * In north_bridge_pin_out_en_high register 13804,
23*b5c850d4SMarcin Wojtas * bit 28 is the one which enables CS, CLK pins to be
24*b5c850d4SMarcin Wojtas * output, need to set it to 1.
25*b5c850d4SMarcin Wojtas * The initial value of this bit is 1, but in UART boot mode
26*b5c850d4SMarcin Wojtas * initialization, this bit is disabled and the SPI CS and CLK pins
27*b5c850d4SMarcin Wojtas * are used for downloading image purpose; so after downloading,
28*b5c850d4SMarcin Wojtas * we should set this bit to 1 again to enable SPI CS and CLK pins.
29*b5c850d4SMarcin Wojtas * And anyway, this bit value should be 1 in all modes,
30*b5c850d4SMarcin Wojtas * so here we does not judge boot mode and set this bit to 1 always.
31*b5c850d4SMarcin Wojtas */
32*b5c850d4SMarcin Wojtas mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG,
33*b5c850d4SMarcin Wojtas 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF);
34*b5c850d4SMarcin Wojtas }
35*b5c850d4SMarcin Wojtas
36*b5c850d4SMarcin Wojtas /* This function overruns the same function in marvell_bl31_setup.c */
bl31_plat_arch_setup(void)37*b5c850d4SMarcin Wojtas void bl31_plat_arch_setup(void)
38*b5c850d4SMarcin Wojtas {
39*b5c850d4SMarcin Wojtas struct dec_win_config *io_dec_map;
40*b5c850d4SMarcin Wojtas uint32_t dec_win_num;
41*b5c850d4SMarcin Wojtas struct dram_win_map dram_wins_map;
42*b5c850d4SMarcin Wojtas
43*b5c850d4SMarcin Wojtas marvell_bl31_plat_arch_setup();
44*b5c850d4SMarcin Wojtas
45*b5c850d4SMarcin Wojtas /* MPP init */
46*b5c850d4SMarcin Wojtas marvell_bl31_mpp_init();
47*b5c850d4SMarcin Wojtas
48*b5c850d4SMarcin Wojtas /* initialize the timer for delay functionality */
49*b5c850d4SMarcin Wojtas plat_delay_timer_init();
50*b5c850d4SMarcin Wojtas
51*b5c850d4SMarcin Wojtas /* CPU address decoder windows initialization. */
52*b5c850d4SMarcin Wojtas cpu_wins_init();
53*b5c850d4SMarcin Wojtas
54*b5c850d4SMarcin Wojtas /* fetch CPU-DRAM window mapping information by reading
55*b5c850d4SMarcin Wojtas * CPU-DRAM decode windows (only the enabled ones)
56*b5c850d4SMarcin Wojtas */
57*b5c850d4SMarcin Wojtas dram_win_map_build(&dram_wins_map);
58*b5c850d4SMarcin Wojtas
59*b5c850d4SMarcin Wojtas /* Get IO address decoder windows */
60*b5c850d4SMarcin Wojtas if (marvell_get_io_dec_win_conf(&io_dec_map, &dec_win_num)) {
61*b5c850d4SMarcin Wojtas printf("No IO address decoder windows configurations found!\n");
62*b5c850d4SMarcin Wojtas return;
63*b5c850d4SMarcin Wojtas }
64*b5c850d4SMarcin Wojtas
65*b5c850d4SMarcin Wojtas /* IO address decoder init */
66*b5c850d4SMarcin Wojtas if (init_io_addr_dec(&dram_wins_map, io_dec_map, dec_win_num)) {
67*b5c850d4SMarcin Wojtas printf("IO address decoder windows initialization failed!\n");
68*b5c850d4SMarcin Wojtas return;
69*b5c850d4SMarcin Wojtas }
70*b5c850d4SMarcin Wojtas }
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