1b5c850d4SMarcin Wojtas /* 2b5c850d4SMarcin Wojtas * Copyright (C) 2018 Marvell International Ltd. 3b5c850d4SMarcin Wojtas * 4b5c850d4SMarcin Wojtas * SPDX-License-Identifier: BSD-3-Clause 5b5c850d4SMarcin Wojtas * https://spdx.org/licenses 6b5c850d4SMarcin Wojtas */ 7b5c850d4SMarcin Wojtas 8b5c850d4SMarcin Wojtas #include <a3700_pm.h> 9b5c850d4SMarcin Wojtas #include <plat_marvell.h> 10b5c850d4SMarcin Wojtas 11*f2800a47SPali Rohár /* This struct provides the PM wake up src configuration for A3720 Development Board */ 12b5c850d4SMarcin Wojtas static struct pm_wake_up_src_config wake_up_src_cfg = { 13b5c850d4SMarcin Wojtas .wake_up_src_num = 3, 14b5c850d4SMarcin Wojtas .wake_up_src[0] = { 15b5c850d4SMarcin Wojtas .wake_up_src_type = WAKE_UP_SRC_GPIO, 16b5c850d4SMarcin Wojtas .wake_up_data = { 17b5c850d4SMarcin Wojtas .gpio_data.bank_num = 0, /* North Bridge */ 18b5c850d4SMarcin Wojtas .gpio_data.gpio_num = 14 19b5c850d4SMarcin Wojtas } 20b5c850d4SMarcin Wojtas }, 21b5c850d4SMarcin Wojtas .wake_up_src[1] = { 22b5c850d4SMarcin Wojtas .wake_up_src_type = WAKE_UP_SRC_GPIO, 23b5c850d4SMarcin Wojtas .wake_up_data = { 24b5c850d4SMarcin Wojtas .gpio_data.bank_num = 1, /* South Bridge */ 25b5c850d4SMarcin Wojtas .gpio_data.gpio_num = 2 26b5c850d4SMarcin Wojtas } 27b5c850d4SMarcin Wojtas }, 28b5c850d4SMarcin Wojtas .wake_up_src[2] = { 29b5c850d4SMarcin Wojtas .wake_up_src_type = WAKE_UP_SRC_UART1, 30b5c850d4SMarcin Wojtas } 31b5c850d4SMarcin Wojtas }; 32b5c850d4SMarcin Wojtas mv_wake_up_src_config_get(void)33b5c850d4SMarcin Wojtasstruct pm_wake_up_src_config *mv_wake_up_src_config_get(void) 34b5c850d4SMarcin Wojtas { 35b5c850d4SMarcin Wojtas return &wake_up_src_cfg; 36b5c850d4SMarcin Wojtas } 37b5c850d4SMarcin Wojtas 38