1 /* 2 * Copyright (c) 2019, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000 8 #define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004 9 #define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c 10 #define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010 11 #define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c 12 #define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020 13 #define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024 14 #define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028 15 #define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c 16 #define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030 17 #define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034 18 #define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040 19 #define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044 20 #define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048 21 #define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050 22 #define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054 23 #define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058 24 #define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c 25 #define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060 26 #define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064 27 #define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068 28 #define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c 29 #define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070 30 31 #define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108 32 #define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c 33 #define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110 34 #define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114 35 #define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118 36 #define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c 37 #define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120 38 #define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c 39 #define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130 40 #define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134 41 #define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138 42 #define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140 43 #define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144 44 #define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148 45 #define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c 46 #define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154 47 #define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158 48 #define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c 49 #define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160 50 #define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164 51 #define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168 52 #define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c 53 #define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170 54 #define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174 55 #define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178 56 #define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190 57 #define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194 58 59 #define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 60 #define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 61 62 #define S10_SYSMGR_CORE(x) (0xffd12000 + (x)) 63 #define SYSMGR_MMC 0x28 64 #define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0) 65 #define SYSMGR_BOOT_SCRATCH_COLD_0 0x200 66 #define SYSMGR_BOOT_SCRATCH_COLD_1 0x204 67 #define SYSMGR_BOOT_SCRATCH_COLD_2 0x208 68 69 70 #define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24)) 71 72 void enable_nonsecure_access(void); 73 74