1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/bl_common.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/ti/uart/uart_16550.h> 14 #include <lib/xlat_tables/xlat_tables.h> 15 #include <lib/mmio.h> 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 #include "socfpga_mailbox.h" 20 #include "socfpga_private.h" 21 #include "socfpga_reset_manager.h" 22 #include "socfpga_system_manager.h" 23 #include "s10_memory_controller.h" 24 #include "s10_pinmux.h" 25 #include "s10_clock_manager.h" 26 27 28 static entry_point_info_t bl32_image_ep_info; 29 static entry_point_info_t bl33_image_ep_info; 30 31 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 32 { 33 entry_point_info_t *next_image_info; 34 35 next_image_info = (type == NON_SECURE) ? 36 &bl33_image_ep_info : &bl32_image_ep_info; 37 38 /* None of the images on this platform can have 0x0 as the entrypoint */ 39 if (next_image_info->pc) 40 return next_image_info; 41 else 42 return NULL; 43 } 44 45 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 46 u_register_t arg2, u_register_t arg3) 47 { 48 static console_t console; 49 50 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); 51 52 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, 53 &console); 54 /* 55 * Check params passed from BL31 should not be NULL, 56 */ 57 void *from_bl2 = (void *) arg0; 58 59 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 60 assert(params_from_bl2 != NULL); 61 62 /* 63 * Copy BL32 (if populated by BL31) and BL33 entry point information. 64 * They are stored in Secure RAM, in BL31's address space. 65 */ 66 67 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 68 params_from_bl2->h.version >= VERSION_2) { 69 70 bl_params_node_t *bl_params = params_from_bl2->head; 71 72 while (bl_params) { 73 if (bl_params->image_id == BL33_IMAGE_ID) 74 bl33_image_ep_info = *bl_params->ep_info; 75 76 bl_params = bl_params->next_params_info; 77 } 78 } else { 79 struct socfpga_bl31_params *arg_from_bl2 = 80 (struct socfpga_bl31_params *) from_bl2; 81 82 assert(arg_from_bl2->h.type == PARAM_BL31); 83 assert(arg_from_bl2->h.version >= VERSION_1); 84 85 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 86 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 87 } 88 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 89 } 90 91 static const interrupt_prop_t s10_interrupt_props[] = { 92 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 93 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 94 }; 95 96 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 97 98 static const gicv2_driver_data_t plat_gicv2_gic_data = { 99 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 100 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 101 .interrupt_props = s10_interrupt_props, 102 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 103 .target_masks = target_mask_array, 104 .target_masks_num = ARRAY_SIZE(target_mask_array), 105 }; 106 107 /******************************************************************************* 108 * Perform any BL3-1 platform setup code 109 ******************************************************************************/ 110 void bl31_platform_setup(void) 111 { 112 socfpga_delay_timer_init(); 113 114 /* Initialize the gic cpu and distributor interfaces */ 115 gicv2_driver_init(&plat_gicv2_gic_data); 116 gicv2_distif_init(); 117 gicv2_pcpu_distif_init(); 118 gicv2_cpuif_enable(); 119 120 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 121 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 122 (uint64_t)plat_secondary_cpus_bl31_entry); 123 124 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 125 } 126 127 const mmap_region_t plat_stratix10_mmap[] = { 128 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 129 MT_MEMORY | MT_RW | MT_NS), 130 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 131 MT_DEVICE | MT_RW | MT_NS), 132 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 133 MT_DEVICE | MT_RW | MT_SECURE), 134 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 135 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 136 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 137 MT_DEVICE | MT_RW | MT_SECURE), 138 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 139 MT_DEVICE | MT_RW | MT_NS), 140 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 141 MT_DEVICE | MT_RW | MT_NS), 142 {0} 143 }; 144 145 /******************************************************************************* 146 * Perform the very early platform specific architectural setup here. At the 147 * moment this is only intializes the mmu in a quick and dirty way. 148 ******************************************************************************/ 149 void bl31_plat_arch_setup(void) 150 { 151 const mmap_region_t bl_regions[] = { 152 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 153 MT_MEMORY | MT_RW | MT_SECURE), 154 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 155 MT_CODE | MT_SECURE), 156 MAP_REGION_FLAT(BL_RO_DATA_BASE, 157 BL_RO_DATA_END - BL_RO_DATA_BASE, 158 MT_RO_DATA | MT_SECURE), 159 #if USE_COHERENT_MEM 160 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 161 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 162 MT_DEVICE | MT_RW | MT_SECURE), 163 #endif 164 {0} 165 }; 166 167 setup_page_tables(bl_regions, plat_stratix10_mmap); 168 enable_mmu_el3(0); 169 } 170 171