1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4 * Copyright (c) 2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <assert.h> 12 #include <common/bl_common.h> 13 #include <drivers/arm/gicv2.h> 14 #include <drivers/ti/uart/uart_16550.h> 15 #include <lib/xlat_tables/xlat_tables.h> 16 #include <lib/mmio.h> 17 #include <plat/common/platform.h> 18 #include <platform_def.h> 19 20 #include "socfpga_mailbox.h" 21 #include "socfpga_noc.h" 22 #include "socfpga_private.h" 23 #include "socfpga_reset_manager.h" 24 #include "socfpga_system_manager.h" 25 #include "s10_memory_controller.h" 26 #include "s10_pinmux.h" 27 #include "s10_clock_manager.h" 28 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 34 { 35 entry_point_info_t *next_image_info; 36 37 next_image_info = (type == NON_SECURE) ? 38 &bl33_image_ep_info : &bl32_image_ep_info; 39 40 /* None of the images on this platform can have 0x0 as the entrypoint */ 41 if (next_image_info->pc) 42 return next_image_info; 43 else 44 return NULL; 45 } 46 47 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 48 u_register_t arg2, u_register_t arg3) 49 { 50 static console_t console; 51 52 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); 53 54 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, 55 PLAT_BAUDRATE, &console); 56 /* 57 * Check params passed from BL31 should not be NULL, 58 */ 59 void *from_bl2 = (void *) arg0; 60 61 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 62 assert(params_from_bl2 != NULL); 63 64 /* 65 * Copy BL32 (if populated by BL31) and BL33 entry point information. 66 * They are stored in Secure RAM, in BL31's address space. 67 */ 68 69 if (params_from_bl2->h.type == PARAM_BL_PARAMS && 70 params_from_bl2->h.version >= VERSION_2) { 71 72 bl_params_node_t *bl_params = params_from_bl2->head; 73 74 while (bl_params) { 75 if (bl_params->image_id == BL33_IMAGE_ID) 76 bl33_image_ep_info = *bl_params->ep_info; 77 78 bl_params = bl_params->next_params_info; 79 } 80 } else { 81 struct socfpga_bl31_params *arg_from_bl2 = 82 (struct socfpga_bl31_params *) from_bl2; 83 84 assert(arg_from_bl2->h.type == PARAM_BL31); 85 assert(arg_from_bl2->h.version >= VERSION_1); 86 87 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 88 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 89 } 90 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 91 } 92 93 static const interrupt_prop_t s10_interrupt_props[] = { 94 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 95 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 96 }; 97 98 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 99 100 static const gicv2_driver_data_t plat_gicv2_gic_data = { 101 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 102 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 103 .interrupt_props = s10_interrupt_props, 104 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 105 .target_masks = target_mask_array, 106 .target_masks_num = ARRAY_SIZE(target_mask_array), 107 }; 108 109 /******************************************************************************* 110 * Perform any BL3-1 platform setup code 111 ******************************************************************************/ 112 void bl31_platform_setup(void) 113 { 114 socfpga_delay_timer_init(); 115 116 /* Initialize the gic cpu and distributor interfaces */ 117 gicv2_driver_init(&plat_gicv2_gic_data); 118 gicv2_distif_init(); 119 gicv2_pcpu_distif_init(); 120 gicv2_cpuif_enable(); 121 122 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ 123 mmio_write_64(PLAT_CPU_RELEASE_ADDR, 124 (uint64_t)plat_secondary_cpus_bl31_entry); 125 126 #if SIP_SVC_V3 127 /* 128 * Re-initialize the mailbox to include V3 specific routines. 129 * In V3, this re-initialize is required because prior to BL31, U-Boot 130 * SPL has its own mailbox settings and this initialization will 131 * override to those settings as required by the V3 framework. 132 */ 133 mailbox_init(); 134 #endif 135 136 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); 137 } 138 139 const mmap_region_t plat_stratix10_mmap[] = { 140 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 141 MT_MEMORY | MT_RW | MT_NS), 142 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 143 MT_DEVICE | MT_RW | MT_NS), 144 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 145 MT_DEVICE | MT_RW | MT_SECURE), 146 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 147 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 148 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 149 MT_DEVICE | MT_RW | MT_SECURE), 150 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 151 MT_DEVICE | MT_RW | MT_NS), 152 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 153 MT_DEVICE | MT_RW | MT_NS), 154 {0} 155 }; 156 157 /******************************************************************************* 158 * Perform the very early platform specific architectural setup here. At the 159 * moment this is only initializes the mmu in a quick and dirty way. 160 ******************************************************************************/ 161 void bl31_plat_arch_setup(void) 162 { 163 const mmap_region_t bl_regions[] = { 164 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 165 MT_MEMORY | MT_RW | MT_SECURE), 166 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 167 MT_CODE | MT_SECURE), 168 MAP_REGION_FLAT(BL_RO_DATA_BASE, 169 BL_RO_DATA_END - BL_RO_DATA_BASE, 170 MT_RO_DATA | MT_SECURE), 171 #if USE_COHERENT_MEM 172 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 173 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 174 MT_DEVICE | MT_RW | MT_SECURE), 175 #endif 176 {0} 177 }; 178 179 setup_page_tables(bl_regions, plat_stratix10_mmap); 180 enable_mmu_el3(0); 181 } 182 183