1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/generic_delay_timer.h> 14 #include <drivers/synopsys/dw_mmc.h> 15 #include <drivers/ti/uart/uart_16550.h> 16 #include <lib/xlat_tables/xlat_tables.h> 17 18 #include "qspi/cadence_qspi.h" 19 #include "socfpga_handoff.h" 20 #include "socfpga_mailbox.h" 21 #include "socfpga_private.h" 22 #include "socfpga_reset_manager.h" 23 #include "socfpga_system_manager.h" 24 #include "s10_clock_manager.h" 25 #include "s10_memory_controller.h" 26 #include "s10_pinmux.h" 27 #include "wdt/watchdog.h" 28 29 30 const mmap_region_t plat_stratix10_mmap[] = { 31 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 32 MT_MEMORY | MT_RW | MT_NS), 33 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 34 MT_DEVICE | MT_RW | MT_NS), 35 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 36 MT_DEVICE | MT_RW | MT_SECURE), 37 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 38 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 39 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 42 MT_DEVICE | MT_RW | MT_NS), 43 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 44 MT_DEVICE | MT_RW | MT_NS), 45 {0}, 46 }; 47 48 boot_source_type boot_source = BOOT_SOURCE; 49 50 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 51 u_register_t x2, u_register_t x4) 52 { 53 static console_16550_t console; 54 handoff reverse_handoff_ptr; 55 56 generic_delay_timer_init(); 57 58 if (socfpga_get_handoff(&reverse_handoff_ptr)) 59 return; 60 config_pinmux(&reverse_handoff_ptr); 61 62 config_clkmgr_handoff(&reverse_handoff_ptr); 63 enable_nonsecure_access(); 64 deassert_peripheral_reset(); 65 config_hps_hs_before_warm_reset(); 66 67 watchdog_init(get_wdt_clk()); 68 69 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, 70 &console); 71 72 socfpga_delay_timer_init(); 73 init_hard_memory_controller(); 74 mailbox_init(); 75 76 if (!intel_mailbox_is_fpga_not_ready()) 77 socfpga_bridges_enable(); 78 } 79 80 81 void bl2_el3_plat_arch_setup(void) 82 { 83 84 struct mmc_device_info info; 85 const mmap_region_t bl_regions[] = { 86 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 87 MT_MEMORY | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 89 MT_CODE | MT_SECURE), 90 MAP_REGION_FLAT(BL_RO_DATA_BASE, 91 BL_RO_DATA_END - BL_RO_DATA_BASE, 92 MT_RO_DATA | MT_SECURE), 93 #if USE_COHERENT_MEM_BAR 94 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 95 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 96 MT_DEVICE | MT_RW | MT_SECURE), 97 #endif 98 {0}, 99 }; 100 101 setup_page_tables(bl_regions, plat_stratix10_mmap); 102 103 enable_mmu_el3(0); 104 105 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 106 107 info.mmc_dev_type = MMC_IS_SD; 108 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 109 110 switch (boot_source) { 111 case BOOT_SOURCE_SDMMC: 112 dw_mmc_init(¶ms, &info); 113 socfpga_io_setup(boot_source); 114 break; 115 116 case BOOT_SOURCE_QSPI: 117 mailbox_set_qspi_open(); 118 mailbox_set_qspi_direct(); 119 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 120 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 121 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 122 socfpga_io_setup(boot_source); 123 break; 124 125 default: 126 ERROR("Unsupported boot source\n"); 127 panic(); 128 break; 129 } 130 } 131 132 uint32_t get_spsr_for_bl33_entry(void) 133 { 134 unsigned long el_status; 135 unsigned int mode; 136 uint32_t spsr; 137 138 /* Figure out what mode we enter the non-secure world in */ 139 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 140 el_status &= ID_AA64PFR0_ELX_MASK; 141 142 mode = (el_status) ? MODE_EL2 : MODE_EL1; 143 144 /* 145 * TODO: Consider the possibility of specifying the SPSR in 146 * the FIP ToC and allowing the platform to have a say as 147 * well. 148 */ 149 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 150 return spsr; 151 } 152 153 154 int bl2_plat_handle_post_image_load(unsigned int image_id) 155 { 156 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 157 158 switch (image_id) { 159 case BL33_IMAGE_ID: 160 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 161 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 162 break; 163 default: 164 break; 165 } 166 167 return 0; 168 } 169 170 /******************************************************************************* 171 * Perform any BL3-1 platform setup code 172 ******************************************************************************/ 173 void bl2_platform_setup(void) 174 { 175 } 176 177