1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <drivers/synopsys/dw_mmc.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/xlat_tables/xlat_tables.h> 18 19 #include "qspi/cadence_qspi.h" 20 #include "socfpga_emac.h" 21 #include "socfpga_handoff.h" 22 #include "socfpga_mailbox.h" 23 #include "socfpga_private.h" 24 #include "socfpga_reset_manager.h" 25 #include "socfpga_system_manager.h" 26 #include "s10_clock_manager.h" 27 #include "s10_memory_controller.h" 28 #include "s10_mmc.h" 29 #include "s10_pinmux.h" 30 #include "wdt/watchdog.h" 31 32 static struct mmc_device_info mmc_info; 33 34 const mmap_region_t plat_stratix10_mmap[] = { 35 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 36 MT_MEMORY | MT_RW | MT_NS), 37 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 38 MT_DEVICE | MT_RW | MT_NS), 39 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 42 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 46 MT_DEVICE | MT_RW | MT_NS), 47 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 48 MT_DEVICE | MT_RW | MT_NS), 49 {0}, 50 }; 51 52 boot_source_type boot_source = BOOT_SOURCE; 53 54 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 55 u_register_t x2, u_register_t x4) 56 { 57 static console_t console; 58 handoff reverse_handoff_ptr; 59 60 generic_delay_timer_init(); 61 62 if (socfpga_get_handoff(&reverse_handoff_ptr)) 63 return; 64 config_pinmux(&reverse_handoff_ptr); 65 66 config_clkmgr_handoff(&reverse_handoff_ptr); 67 enable_nonsecure_access(); 68 deassert_peripheral_reset(); 69 config_hps_hs_before_warm_reset(); 70 71 watchdog_init(get_wdt_clk()); 72 73 console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(), 74 PLAT_BAUDRATE, &console); 75 76 socfpga_emac_init(); 77 socfpga_delay_timer_init(); 78 init_hard_memory_controller(); 79 mailbox_init(); 80 s10_mmc_init(); 81 82 if (!intel_mailbox_is_fpga_not_ready()) 83 socfpga_bridges_enable(); 84 } 85 86 87 void bl2_el3_plat_arch_setup(void) 88 { 89 90 const mmap_region_t bl_regions[] = { 91 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 92 MT_MEMORY | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 94 MT_CODE | MT_SECURE), 95 MAP_REGION_FLAT(BL_RO_DATA_BASE, 96 BL_RO_DATA_END - BL_RO_DATA_BASE, 97 MT_RO_DATA | MT_SECURE), 98 #if USE_COHERENT_MEM_BAR 99 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 100 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 101 MT_DEVICE | MT_RW | MT_SECURE), 102 #endif 103 {0}, 104 }; 105 106 setup_page_tables(bl_regions, plat_stratix10_mmap); 107 108 enable_mmu_el3(0); 109 110 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 111 112 mmc_info.mmc_dev_type = MMC_IS_SD; 113 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 114 115 /* Request ownership and direct access to QSPI */ 116 mailbox_hps_qspi_enable(); 117 118 switch (boot_source) { 119 case BOOT_SOURCE_SDMMC: 120 dw_mmc_init(¶ms, &mmc_info); 121 socfpga_io_setup(boot_source); 122 break; 123 124 case BOOT_SOURCE_QSPI: 125 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 126 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 127 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 128 socfpga_io_setup(boot_source); 129 break; 130 131 default: 132 ERROR("Unsupported boot source\n"); 133 panic(); 134 break; 135 } 136 } 137 138 uint32_t get_spsr_for_bl33_entry(void) 139 { 140 unsigned long el_status; 141 unsigned int mode; 142 uint32_t spsr; 143 144 /* Figure out what mode we enter the non-secure world in */ 145 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 146 el_status &= ID_AA64PFR0_ELX_MASK; 147 148 mode = (el_status) ? MODE_EL2 : MODE_EL1; 149 150 /* 151 * TODO: Consider the possibility of specifying the SPSR in 152 * the FIP ToC and allowing the platform to have a say as 153 * well. 154 */ 155 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 156 return spsr; 157 } 158 159 160 int bl2_plat_handle_post_image_load(unsigned int image_id) 161 { 162 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 163 164 assert(bl_mem_params); 165 166 switch (image_id) { 167 case BL33_IMAGE_ID: 168 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 169 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 170 break; 171 default: 172 break; 173 } 174 175 return 0; 176 } 177 178 /******************************************************************************* 179 * Perform any BL3-1 platform setup code 180 ******************************************************************************/ 181 void bl2_platform_setup(void) 182 { 183 } 184 185