19d82ef26SLoh Tien Hock /* 29d82ef26SLoh Tien Hock * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 39d82ef26SLoh Tien Hock * 49d82ef26SLoh Tien Hock * SPDX-License-Identifier: BSD-3-Clause 59d82ef26SLoh Tien Hock */ 69d82ef26SLoh Tien Hock 79d82ef26SLoh Tien Hock #include <arch.h> 89d82ef26SLoh Tien Hock #include <arch_helpers.h> 99d82ef26SLoh Tien Hock #include <drivers/arm/gicv2.h> 109d82ef26SLoh Tien Hock 119d82ef26SLoh Tien Hock #include <drivers/generic_delay_timer.h> 129d82ef26SLoh Tien Hock #include <drivers/console.h> 139d82ef26SLoh Tien Hock #include <drivers/ti/uart/uart_16550.h> 149d82ef26SLoh Tien Hock #include <common/bl_common.h> 159d82ef26SLoh Tien Hock #include <common/debug.h> 169d82ef26SLoh Tien Hock #include <common/desc_image_load.h> 179d82ef26SLoh Tien Hock #include <errno.h> 189d82ef26SLoh Tien Hock #include <drivers/io/io_storage.h> 199d82ef26SLoh Tien Hock #include <common/image_decompress.h> 209d82ef26SLoh Tien Hock #include <plat/common/platform.h> 219d82ef26SLoh Tien Hock #include <platform_def.h> 229d82ef26SLoh Tien Hock #include <platform_private.h> 239d82ef26SLoh Tien Hock #include <drivers/synopsys/dw_mmc.h> 249d82ef26SLoh Tien Hock #include <lib/mmio.h> 259d82ef26SLoh Tien Hock #include <lib/xlat_tables/xlat_tables.h> 269d82ef26SLoh Tien Hock 279d82ef26SLoh Tien Hock #include "s10_memory_controller.h" 289d82ef26SLoh Tien Hock #include "s10_reset_manager.h" 299d82ef26SLoh Tien Hock #include "s10_clock_manager.h" 309d82ef26SLoh Tien Hock #include "s10_handoff.h" 319d82ef26SLoh Tien Hock #include "s10_pinmux.h" 329d82ef26SLoh Tien Hock #include "aarch64/stratix10_private.h" 339d82ef26SLoh Tien Hock 349d82ef26SLoh Tien Hock const mmap_region_t plat_stratix10_mmap[] = { 359d82ef26SLoh Tien Hock MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), 369d82ef26SLoh Tien Hock MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), 379d82ef26SLoh Tien Hock MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS), 389d82ef26SLoh Tien Hock MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 399d82ef26SLoh Tien Hock MT_NON_CACHEABLE | MT_RW | MT_SECURE), 409d82ef26SLoh Tien Hock MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 419d82ef26SLoh Tien Hock MT_DEVICE | MT_RW | MT_SECURE), 429d82ef26SLoh Tien Hock MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), 439d82ef26SLoh Tien Hock MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), 449d82ef26SLoh Tien Hock {0}, 459d82ef26SLoh Tien Hock }; 469d82ef26SLoh Tien Hock 479d82ef26SLoh Tien Hock boot_source_type boot_source; 489d82ef26SLoh Tien Hock 499d82ef26SLoh Tien Hock void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 509d82ef26SLoh Tien Hock u_register_t x2, u_register_t x4) 519d82ef26SLoh Tien Hock { 529d82ef26SLoh Tien Hock static console_16550_t console; 539d82ef26SLoh Tien Hock handoff reverse_handoff_ptr; 549d82ef26SLoh Tien Hock 559d82ef26SLoh Tien Hock generic_delay_timer_init(); 569d82ef26SLoh Tien Hock 579d82ef26SLoh Tien Hock if (s10_get_handoff(&reverse_handoff_ptr)) 589d82ef26SLoh Tien Hock return; 599d82ef26SLoh Tien Hock config_pinmux(&reverse_handoff_ptr); 609d82ef26SLoh Tien Hock boot_source = reverse_handoff_ptr.boot_source; 619d82ef26SLoh Tien Hock 629d82ef26SLoh Tien Hock config_clkmgr_handoff(&reverse_handoff_ptr); 639d82ef26SLoh Tien Hock enable_nonsecure_access(); 649d82ef26SLoh Tien Hock deassert_peripheral_reset(); 659d82ef26SLoh Tien Hock config_hps_hs_before_warm_reset(); 669d82ef26SLoh Tien Hock 679d82ef26SLoh Tien Hock console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, 689d82ef26SLoh Tien Hock &console); 699d82ef26SLoh Tien Hock 709d82ef26SLoh Tien Hock plat_delay_timer_init(); 719d82ef26SLoh Tien Hock init_hard_memory_controller(); 729d82ef26SLoh Tien Hock } 739d82ef26SLoh Tien Hock 749d82ef26SLoh Tien Hock 759d82ef26SLoh Tien Hock void bl2_el3_plat_arch_setup(void) 769d82ef26SLoh Tien Hock { 779d82ef26SLoh Tien Hock 789d82ef26SLoh Tien Hock struct mmc_device_info info; 799d82ef26SLoh Tien Hock const mmap_region_t bl_regions[] = { 809d82ef26SLoh Tien Hock MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 819d82ef26SLoh Tien Hock MT_MEMORY | MT_RW | MT_SECURE), 829d82ef26SLoh Tien Hock MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 839d82ef26SLoh Tien Hock MT_CODE | MT_SECURE), 849d82ef26SLoh Tien Hock MAP_REGION_FLAT(BL_RO_DATA_BASE, 859d82ef26SLoh Tien Hock BL_RO_DATA_END - BL_RO_DATA_BASE, 869d82ef26SLoh Tien Hock MT_RO_DATA | MT_SECURE), 879d82ef26SLoh Tien Hock #if USE_COHERENT_MEM_BAR 889d82ef26SLoh Tien Hock MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 899d82ef26SLoh Tien Hock BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 909d82ef26SLoh Tien Hock MT_DEVICE | MT_RW | MT_SECURE), 919d82ef26SLoh Tien Hock #endif 929d82ef26SLoh Tien Hock {0}, 939d82ef26SLoh Tien Hock }; 949d82ef26SLoh Tien Hock 959d82ef26SLoh Tien Hock setup_page_tables(bl_regions, plat_stratix10_mmap); 969d82ef26SLoh Tien Hock 979d82ef26SLoh Tien Hock enable_mmu_el3(0); 989d82ef26SLoh Tien Hock 999d82ef26SLoh Tien Hock dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000); 1009d82ef26SLoh Tien Hock 1019d82ef26SLoh Tien Hock info.mmc_dev_type = MMC_IS_SD; 102*dd8c03b6STien Hock, Loh info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 1039d82ef26SLoh Tien Hock 1049d82ef26SLoh Tien Hock switch (boot_source) { 1059d82ef26SLoh Tien Hock case BOOT_SOURCE_SDMMC: 1069d82ef26SLoh Tien Hock dw_mmc_init(¶ms, &info); 1079d82ef26SLoh Tien Hock stratix10_io_setup(); 1089d82ef26SLoh Tien Hock break; 1099d82ef26SLoh Tien Hock default: 1109d82ef26SLoh Tien Hock ERROR("Unsupported boot source\n"); 1119d82ef26SLoh Tien Hock panic(); 1129d82ef26SLoh Tien Hock break; 1139d82ef26SLoh Tien Hock } 1149d82ef26SLoh Tien Hock } 1159d82ef26SLoh Tien Hock 1169d82ef26SLoh Tien Hock uint32_t get_spsr_for_bl33_entry(void) 1179d82ef26SLoh Tien Hock { 1189d82ef26SLoh Tien Hock unsigned long el_status; 1199d82ef26SLoh Tien Hock unsigned int mode; 1209d82ef26SLoh Tien Hock uint32_t spsr; 1219d82ef26SLoh Tien Hock 1229d82ef26SLoh Tien Hock /* Figure out what mode we enter the non-secure world in */ 1239d82ef26SLoh Tien Hock el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 1249d82ef26SLoh Tien Hock el_status &= ID_AA64PFR0_ELX_MASK; 1259d82ef26SLoh Tien Hock 1269d82ef26SLoh Tien Hock mode = (el_status) ? MODE_EL2 : MODE_EL1; 1279d82ef26SLoh Tien Hock 1289d82ef26SLoh Tien Hock /* 1299d82ef26SLoh Tien Hock * TODO: Consider the possibility of specifying the SPSR in 1309d82ef26SLoh Tien Hock * the FIP ToC and allowing the platform to have a say as 1319d82ef26SLoh Tien Hock * well. 1329d82ef26SLoh Tien Hock */ 1339d82ef26SLoh Tien Hock spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 1349d82ef26SLoh Tien Hock return spsr; 1359d82ef26SLoh Tien Hock } 1369d82ef26SLoh Tien Hock 1379d82ef26SLoh Tien Hock 1389d82ef26SLoh Tien Hock int bl2_plat_handle_post_image_load(unsigned int image_id) 1399d82ef26SLoh Tien Hock { 1409d82ef26SLoh Tien Hock bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 1419d82ef26SLoh Tien Hock 1429d82ef26SLoh Tien Hock switch (image_id) { 1439d82ef26SLoh Tien Hock case BL33_IMAGE_ID: 1449d82ef26SLoh Tien Hock bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 1459d82ef26SLoh Tien Hock bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 1469d82ef26SLoh Tien Hock break; 1479d82ef26SLoh Tien Hock default: 1489d82ef26SLoh Tien Hock break; 1499d82ef26SLoh Tien Hock } 1509d82ef26SLoh Tien Hock 1519d82ef26SLoh Tien Hock return 0; 1529d82ef26SLoh Tien Hock } 1539d82ef26SLoh Tien Hock 1549d82ef26SLoh Tien Hock /******************************************************************************* 1559d82ef26SLoh Tien Hock * Perform any BL3-1 platform setup code 1569d82ef26SLoh Tien Hock ******************************************************************************/ 1579d82ef26SLoh Tien Hock void bl2_platform_setup(void) 1589d82ef26SLoh Tien Hock { 1599d82ef26SLoh Tien Hock } 1609d82ef26SLoh Tien Hock 161