xref: /rk3399_ARM-atf/plat/intel/soc/stratix10/bl2_plat_setup.c (revision 9d82ef26c657fda9ee21806817c7a16547b0b605)
1*9d82ef26SLoh Tien Hock /*
2*9d82ef26SLoh Tien Hock  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*9d82ef26SLoh Tien Hock  *
4*9d82ef26SLoh Tien Hock  * SPDX-License-Identifier: BSD-3-Clause
5*9d82ef26SLoh Tien Hock  */
6*9d82ef26SLoh Tien Hock 
7*9d82ef26SLoh Tien Hock #include <arch.h>
8*9d82ef26SLoh Tien Hock #include <arch_helpers.h>
9*9d82ef26SLoh Tien Hock #include <drivers/arm/gicv2.h>
10*9d82ef26SLoh Tien Hock 
11*9d82ef26SLoh Tien Hock #include <drivers/generic_delay_timer.h>
12*9d82ef26SLoh Tien Hock #include <drivers/console.h>
13*9d82ef26SLoh Tien Hock #include <drivers/ti/uart/uart_16550.h>
14*9d82ef26SLoh Tien Hock #include <common/bl_common.h>
15*9d82ef26SLoh Tien Hock #include <common/debug.h>
16*9d82ef26SLoh Tien Hock #include <common/desc_image_load.h>
17*9d82ef26SLoh Tien Hock #include <errno.h>
18*9d82ef26SLoh Tien Hock #include <drivers/io/io_storage.h>
19*9d82ef26SLoh Tien Hock #include <common/image_decompress.h>
20*9d82ef26SLoh Tien Hock #include <plat/common/platform.h>
21*9d82ef26SLoh Tien Hock #include <platform_def.h>
22*9d82ef26SLoh Tien Hock #include <platform_private.h>
23*9d82ef26SLoh Tien Hock #include <drivers/synopsys/dw_mmc.h>
24*9d82ef26SLoh Tien Hock #include <lib/mmio.h>
25*9d82ef26SLoh Tien Hock #include <lib/xlat_tables/xlat_tables.h>
26*9d82ef26SLoh Tien Hock 
27*9d82ef26SLoh Tien Hock #include "s10_memory_controller.h"
28*9d82ef26SLoh Tien Hock #include "s10_reset_manager.h"
29*9d82ef26SLoh Tien Hock #include "s10_clock_manager.h"
30*9d82ef26SLoh Tien Hock #include "s10_handoff.h"
31*9d82ef26SLoh Tien Hock #include "s10_pinmux.h"
32*9d82ef26SLoh Tien Hock #include "aarch64/stratix10_private.h"
33*9d82ef26SLoh Tien Hock 
34*9d82ef26SLoh Tien Hock const mmap_region_t plat_stratix10_mmap[] = {
35*9d82ef26SLoh Tien Hock 	MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
36*9d82ef26SLoh Tien Hock 	MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
37*9d82ef26SLoh Tien Hock 	MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS),
38*9d82ef26SLoh Tien Hock 	MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
39*9d82ef26SLoh Tien Hock 		MT_NON_CACHEABLE | MT_RW | MT_SECURE),
40*9d82ef26SLoh Tien Hock 	MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
41*9d82ef26SLoh Tien Hock 		MT_DEVICE | MT_RW | MT_SECURE),
42*9d82ef26SLoh Tien Hock 	MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
43*9d82ef26SLoh Tien Hock 	MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
44*9d82ef26SLoh Tien Hock 	{0},
45*9d82ef26SLoh Tien Hock };
46*9d82ef26SLoh Tien Hock 
47*9d82ef26SLoh Tien Hock boot_source_type boot_source;
48*9d82ef26SLoh Tien Hock 
49*9d82ef26SLoh Tien Hock void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
50*9d82ef26SLoh Tien Hock 				u_register_t x2, u_register_t x4)
51*9d82ef26SLoh Tien Hock {
52*9d82ef26SLoh Tien Hock 	static console_16550_t console;
53*9d82ef26SLoh Tien Hock 	handoff reverse_handoff_ptr;
54*9d82ef26SLoh Tien Hock 
55*9d82ef26SLoh Tien Hock 	generic_delay_timer_init();
56*9d82ef26SLoh Tien Hock 
57*9d82ef26SLoh Tien Hock 	if (s10_get_handoff(&reverse_handoff_ptr))
58*9d82ef26SLoh Tien Hock 		return;
59*9d82ef26SLoh Tien Hock 	config_pinmux(&reverse_handoff_ptr);
60*9d82ef26SLoh Tien Hock 	boot_source = reverse_handoff_ptr.boot_source;
61*9d82ef26SLoh Tien Hock 
62*9d82ef26SLoh Tien Hock 	config_clkmgr_handoff(&reverse_handoff_ptr);
63*9d82ef26SLoh Tien Hock 	enable_nonsecure_access();
64*9d82ef26SLoh Tien Hock 	deassert_peripheral_reset();
65*9d82ef26SLoh Tien Hock 	config_hps_hs_before_warm_reset();
66*9d82ef26SLoh Tien Hock 
67*9d82ef26SLoh Tien Hock 	console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
68*9d82ef26SLoh Tien Hock 		&console);
69*9d82ef26SLoh Tien Hock 
70*9d82ef26SLoh Tien Hock 	plat_delay_timer_init();
71*9d82ef26SLoh Tien Hock 	init_hard_memory_controller();
72*9d82ef26SLoh Tien Hock }
73*9d82ef26SLoh Tien Hock 
74*9d82ef26SLoh Tien Hock 
75*9d82ef26SLoh Tien Hock void bl2_el3_plat_arch_setup(void)
76*9d82ef26SLoh Tien Hock {
77*9d82ef26SLoh Tien Hock 
78*9d82ef26SLoh Tien Hock 	struct mmc_device_info info;
79*9d82ef26SLoh Tien Hock 	const mmap_region_t bl_regions[] = {
80*9d82ef26SLoh Tien Hock 		MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
81*9d82ef26SLoh Tien Hock 			MT_MEMORY | MT_RW | MT_SECURE),
82*9d82ef26SLoh Tien Hock 		MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
83*9d82ef26SLoh Tien Hock 			MT_CODE | MT_SECURE),
84*9d82ef26SLoh Tien Hock 		MAP_REGION_FLAT(BL_RO_DATA_BASE,
85*9d82ef26SLoh Tien Hock 			BL_RO_DATA_END - BL_RO_DATA_BASE,
86*9d82ef26SLoh Tien Hock 			MT_RO_DATA | MT_SECURE),
87*9d82ef26SLoh Tien Hock #if USE_COHERENT_MEM_BAR
88*9d82ef26SLoh Tien Hock 		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
89*9d82ef26SLoh Tien Hock 			BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
90*9d82ef26SLoh Tien Hock 			MT_DEVICE | MT_RW | MT_SECURE),
91*9d82ef26SLoh Tien Hock #endif
92*9d82ef26SLoh Tien Hock 		{0},
93*9d82ef26SLoh Tien Hock 	};
94*9d82ef26SLoh Tien Hock 
95*9d82ef26SLoh Tien Hock 	setup_page_tables(bl_regions, plat_stratix10_mmap);
96*9d82ef26SLoh Tien Hock 
97*9d82ef26SLoh Tien Hock 	enable_mmu_el3(0);
98*9d82ef26SLoh Tien Hock 
99*9d82ef26SLoh Tien Hock 	/* ECC Scrubbing */
100*9d82ef26SLoh Tien Hock 	memset(0, DRAM_BASE, DRAM_SIZE);
101*9d82ef26SLoh Tien Hock 
102*9d82ef26SLoh Tien Hock 	dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
103*9d82ef26SLoh Tien Hock 
104*9d82ef26SLoh Tien Hock 	info.mmc_dev_type = MMC_IS_SD;
105*9d82ef26SLoh Tien Hock 
106*9d82ef26SLoh Tien Hock 	switch (boot_source) {
107*9d82ef26SLoh Tien Hock 	case BOOT_SOURCE_SDMMC:
108*9d82ef26SLoh Tien Hock 		dw_mmc_init(&params, &info);
109*9d82ef26SLoh Tien Hock 		stratix10_io_setup();
110*9d82ef26SLoh Tien Hock 		break;
111*9d82ef26SLoh Tien Hock 	default:
112*9d82ef26SLoh Tien Hock 		ERROR("Unsupported boot source\n");
113*9d82ef26SLoh Tien Hock 		panic();
114*9d82ef26SLoh Tien Hock 		break;
115*9d82ef26SLoh Tien Hock 	}
116*9d82ef26SLoh Tien Hock }
117*9d82ef26SLoh Tien Hock 
118*9d82ef26SLoh Tien Hock uint32_t get_spsr_for_bl33_entry(void)
119*9d82ef26SLoh Tien Hock {
120*9d82ef26SLoh Tien Hock 	unsigned long el_status;
121*9d82ef26SLoh Tien Hock 	unsigned int mode;
122*9d82ef26SLoh Tien Hock 	uint32_t spsr;
123*9d82ef26SLoh Tien Hock 
124*9d82ef26SLoh Tien Hock 	/* Figure out what mode we enter the non-secure world in */
125*9d82ef26SLoh Tien Hock 	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
126*9d82ef26SLoh Tien Hock 	el_status &= ID_AA64PFR0_ELX_MASK;
127*9d82ef26SLoh Tien Hock 
128*9d82ef26SLoh Tien Hock 	mode = (el_status) ? MODE_EL2 : MODE_EL1;
129*9d82ef26SLoh Tien Hock 
130*9d82ef26SLoh Tien Hock 	/*
131*9d82ef26SLoh Tien Hock 	 * TODO: Consider the possibility of specifying the SPSR in
132*9d82ef26SLoh Tien Hock 	 * the FIP ToC and allowing the platform to have a say as
133*9d82ef26SLoh Tien Hock 	 * well.
134*9d82ef26SLoh Tien Hock 	 */
135*9d82ef26SLoh Tien Hock 	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
136*9d82ef26SLoh Tien Hock 	return spsr;
137*9d82ef26SLoh Tien Hock }
138*9d82ef26SLoh Tien Hock 
139*9d82ef26SLoh Tien Hock 
140*9d82ef26SLoh Tien Hock int bl2_plat_handle_post_image_load(unsigned int image_id)
141*9d82ef26SLoh Tien Hock {
142*9d82ef26SLoh Tien Hock 	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
143*9d82ef26SLoh Tien Hock 
144*9d82ef26SLoh Tien Hock 	switch (image_id) {
145*9d82ef26SLoh Tien Hock 	case BL33_IMAGE_ID:
146*9d82ef26SLoh Tien Hock 		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
147*9d82ef26SLoh Tien Hock 		bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
148*9d82ef26SLoh Tien Hock 		break;
149*9d82ef26SLoh Tien Hock 	default:
150*9d82ef26SLoh Tien Hock 		break;
151*9d82ef26SLoh Tien Hock 	}
152*9d82ef26SLoh Tien Hock 
153*9d82ef26SLoh Tien Hock 	return 0;
154*9d82ef26SLoh Tien Hock }
155*9d82ef26SLoh Tien Hock 
156*9d82ef26SLoh Tien Hock /*******************************************************************************
157*9d82ef26SLoh Tien Hock  * Perform any BL3-1 platform setup code
158*9d82ef26SLoh Tien Hock  ******************************************************************************/
159*9d82ef26SLoh Tien Hock void bl2_platform_setup(void)
160*9d82ef26SLoh Tien Hock {
161*9d82ef26SLoh Tien Hock }
162*9d82ef26SLoh Tien Hock 
163