1# 2# Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3# Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6# 7 8PLAT_INCLUDES := \ 9 -Iplat/intel/soc/n5x/include/ \ 10 -Iplat/intel/soc/common/drivers/ \ 11 -Iplat/intel/soc/common/include/ 12 13# Include GICv2 driver files 14include drivers/arm/gic/v2/gicv2.mk 15DM_GICv2_SOURCES := \ 16 ${GICV2_SOURCES} \ 17 plat/common/plat_gicv2.c 18 19 20PLAT_BL_COMMON_SOURCES := \ 21 ${DM_GICv2_SOURCES} \ 22 drivers/delay_timer/delay_timer.c \ 23 drivers/delay_timer/generic_delay_timer.c \ 24 drivers/ti/uart/aarch64/16550_console.S \ 25 lib/xlat_tables/aarch64/xlat_tables.c \ 26 lib/xlat_tables/xlat_tables_common.c \ 27 plat/intel/soc/common/aarch64/platform_common.c \ 28 plat/intel/soc/common/aarch64/plat_helpers.S \ 29 plat/intel/soc/common/socfpga_delay_timer.c \ 30 plat/intel/soc/common/drivers/ccu/ncore_ccu.c 31 32BL2_SOURCES += 33 34BL31_SOURCES += \ 35 drivers/arm/cci/cci.c \ 36 lib/cpus/aarch64/aem_generic.S \ 37 lib/cpus/aarch64/cortex_a53.S \ 38 plat/common/plat_psci_common.c \ 39 plat/intel/soc/n5x/bl31_plat_setup.c \ 40 plat/intel/soc/n5x/soc/n5x_clock_manager.c \ 41 plat/intel/soc/common/socfpga_psci.c \ 42 plat/intel/soc/common/socfpga_sip_svc.c \ 43 plat/intel/soc/common/socfpga_sip_svc_v2.c \ 44 plat/intel/soc/common/socfpga_topology.c \ 45 plat/intel/soc/common/sip/socfpga_sip_ecc.c \ 46 plat/intel/soc/common/sip/socfpga_sip_fcs.c \ 47 plat/intel/soc/common/soc/socfpga_mailbox.c \ 48 plat/intel/soc/common/soc/socfpga_reset_manager.c 49 50# Don't have the Linux kernel as a BL33 image by default 51ARM_LINUX_KERNEL_AS_BL33 := 0 52$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33)) 53$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33)) 54$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) 55 56# Configs for Boot Source 57SOCFPGA_BOOT_SOURCE_SDMMC ?= 0 58SOCFPGA_BOOT_SOURCE_QSPI ?= 0 59SOCFPGA_BOOT_SOURCE_NAND ?= 0 60 61$(eval $(call assert_booleans,\ 62 $(sort \ 63 SOCFPGA_BOOT_SOURCE_SDMMC \ 64 SOCFPGA_BOOT_SOURCE_QSPI \ 65 SOCFPGA_BOOT_SOURCE_NAND \ 66))) 67$(eval $(call add_defines,\ 68 $(sort \ 69 SOCFPGA_BOOT_SOURCE_SDMMC \ 70 SOCFPGA_BOOT_SOURCE_QSPI \ 71 SOCFPGA_BOOT_SOURCE_NAND \ 72))) 73 74PROGRAMMABLE_RESET_ADDRESS := 0 75RESET_TO_BL2 := 1 76BL2_INV_DCACHE := 0 77USE_COHERENT_MEM := 1 78 79#To get the TF-A version via SMC calls 80DEFINES += -DVERSION_MAJOR=${VERSION_MAJOR} 81DEFINES += -DVERSION_MINOR=${VERSION_MINOR} 82DEFINES += -DVERSION_PATCH=${VERSION_PATCH} 83