1*325eb35dSSieu Mun Tang# 2*325eb35dSSieu Mun Tang# Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3*325eb35dSSieu Mun Tang# 4*325eb35dSSieu Mun Tang# SPDX-License-Identifier: BSD-3-Clause 5*325eb35dSSieu Mun Tang# 6*325eb35dSSieu Mun Tang 7*325eb35dSSieu Mun TangPLAT_INCLUDES := \ 8*325eb35dSSieu Mun Tang -Iplat/intel/soc/n5x/include/ \ 9*325eb35dSSieu Mun Tang -Iplat/intel/soc/common/drivers/ \ 10*325eb35dSSieu Mun Tang -Iplat/intel/soc/common/include/ 11*325eb35dSSieu Mun Tang 12*325eb35dSSieu Mun Tang# Include GICv2 driver files 13*325eb35dSSieu Mun Tanginclude drivers/arm/gic/v2/gicv2.mk 14*325eb35dSSieu Mun TangDM_GICv2_SOURCES := \ 15*325eb35dSSieu Mun Tang ${GICV2_SOURCES} \ 16*325eb35dSSieu Mun Tang plat/common/plat_gicv2.c 17*325eb35dSSieu Mun Tang 18*325eb35dSSieu Mun Tang 19*325eb35dSSieu Mun TangPLAT_BL_COMMON_SOURCES := \ 20*325eb35dSSieu Mun Tang ${DM_GICv2_SOURCES} \ 21*325eb35dSSieu Mun Tang drivers/delay_timer/delay_timer.c \ 22*325eb35dSSieu Mun Tang drivers/delay_timer/generic_delay_timer.c \ 23*325eb35dSSieu Mun Tang drivers/ti/uart/aarch64/16550_console.S \ 24*325eb35dSSieu Mun Tang lib/xlat_tables/aarch64/xlat_tables.c \ 25*325eb35dSSieu Mun Tang lib/xlat_tables/xlat_tables_common.c \ 26*325eb35dSSieu Mun Tang plat/intel/soc/common/aarch64/platform_common.c \ 27*325eb35dSSieu Mun Tang plat/intel/soc/common/aarch64/plat_helpers.S \ 28*325eb35dSSieu Mun Tang plat/intel/soc/common/socfpga_delay_timer.c 29*325eb35dSSieu Mun Tang 30*325eb35dSSieu Mun TangBL2_SOURCES += 31*325eb35dSSieu Mun Tang 32*325eb35dSSieu Mun TangBL31_SOURCES += \ 33*325eb35dSSieu Mun Tang drivers/arm/cci/cci.c \ 34*325eb35dSSieu Mun Tang lib/cpus/aarch64/aem_generic.S \ 35*325eb35dSSieu Mun Tang lib/cpus/aarch64/cortex_a53.S \ 36*325eb35dSSieu Mun Tang plat/common/plat_psci_common.c \ 37*325eb35dSSieu Mun Tang plat/intel/soc/n5x/bl31_plat_setup.c \ 38*325eb35dSSieu Mun Tang plat/intel/soc/common/socfpga_psci.c \ 39*325eb35dSSieu Mun Tang plat/intel/soc/common/socfpga_sip_svc.c \ 40*325eb35dSSieu Mun Tang plat/intel/soc/common/socfpga_topology.c \ 41*325eb35dSSieu Mun Tang plat/intel/soc/common/sip/socfpga_sip_fcs.c \ 42*325eb35dSSieu Mun Tang plat/intel/soc/common/soc/socfpga_mailbox.c \ 43*325eb35dSSieu Mun Tang plat/intel/soc/common/soc/socfpga_reset_manager.c 44*325eb35dSSieu Mun Tang 45*325eb35dSSieu Mun TangPROGRAMMABLE_RESET_ADDRESS := 0 46*325eb35dSSieu Mun TangBL2_AT_EL3 := 1 47*325eb35dSSieu Mun TangBL2_INV_DCACHE := 0 48*325eb35dSSieu Mun TangMULTI_CONSOLE_API := 1 49*325eb35dSSieu Mun TangUSE_COHERENT_MEM := 1 50