1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_SOCFPGA_DEF_H 8 #define PLAT_SOCFPGA_DEF_H 9 10 #include <platform_def.h> 11 12 /* Platform Setting */ 13 #define PLATFORM_MODEL PLAT_SOCFPGA_N5X 14 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 15 16 /* Register Mapping */ 17 #define SOCFPGA_MMC_REG_BASE U(0xff808000) 18 19 #define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000) 20 #define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000) 21 22 #define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000) 23 #define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100) 24 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200) 25 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) 26 27 #endif /* PLAT_SOCFPGA_DEF_H */ 28