1 /* 2 * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLAT_SOCFPGA_DEF_H 9 #define PLAT_SOCFPGA_DEF_H 10 11 #include <platform_def.h> 12 #include "n5x_system_manager.h" 13 14 /* Platform Setting */ 15 #define PLATFORM_MODEL PLAT_SOCFPGA_N5X 16 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 17 #define PLAT_PRIMARY_CPU 0 18 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 19 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT 20 21 /* FPGA config helpers */ 22 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 23 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 24 25 /* QSPI Setting */ 26 #define CAD_QSPIDATA_OFST 0xff900000 27 #define CAD_QSPI_OFFSET 0xff8d2000 28 29 /* Register Mapping */ 30 #define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000) 31 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 32 #define SOCFPGA_MMC_REG_BASE U(0xff808000) 33 #define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000) 34 #define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000) 35 #define SOCFPGA_ECC_QSPI_REG_BASE U(0xffa22000) 36 37 #define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000) 38 #define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100) 39 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200) 40 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) 41 42 43 /******************************************************************************* 44 * Platform memory map related constants 45 ******************************************************************************/ 46 #define DRAM_BASE (0x0) 47 #define DRAM_SIZE (0x80000000) 48 49 #define OCRAM_BASE (0xFFE00000) 50 #define OCRAM_SIZE (0x00040000) 51 52 #define MEM64_BASE (0x0100000000) 53 #define MEM64_SIZE (0x1F00000000) 54 55 #define DEVICE1_BASE (0x80000000) 56 #define DEVICE1_SIZE (0x60000000) 57 58 #define DEVICE2_BASE (0xF7000000) 59 #define DEVICE2_SIZE (0x08E00000) 60 61 #define DEVICE3_BASE (0xFFFC0000) 62 #define DEVICE3_SIZE (0x00008000) 63 64 #define DEVICE4_BASE (0x2000000000) 65 #define DEVICE4_SIZE (0x0100000000) 66 67 #define BL2_BASE (0xffe00000) 68 #define BL2_LIMIT (0xffe1b000) 69 70 #define BL31_BASE (0x1000) 71 #define BL31_LIMIT (0x81000) 72 73 /******************************************************************************* 74 * UART related constants 75 ******************************************************************************/ 76 #define PLAT_UART0_BASE (0xFFC02000) 77 #define PLAT_UART1_BASE (0xFFC02100) 78 79 /******************************************************************************* 80 * WDT related constants 81 ******************************************************************************/ 82 #define WDT_BASE (0xFFD00200) 83 84 /******************************************************************************* 85 * GIC related constants 86 ******************************************************************************/ 87 #define PLAT_GIC_BASE (0xFFFC0000) 88 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 89 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 90 #define PLAT_GICR_BASE 0 91 92 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ) 93 #define PLAT_HZ_CONVERT_TO_MHZ (1000000) 94 95 /******************************************************************************* 96 * SDMMC related pointer function 97 ******************************************************************************/ 98 #define SDMMC_READ_BLOCKS mmc_read_blocks 99 #define SDMMC_WRITE_BLOCKS mmc_write_blocks 100 101 /******************************************************************************* 102 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 103 * is done and HPS should trigger warm reset via RMR_EL3. 104 ******************************************************************************/ 105 #define L2_RESET_DONE_REG 0xFFD12218 106 107 /* Platform specific system counter */ 108 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk() 109 110 #endif /* PLAT_SOCFPGA_DEF_H */ 111