1 /* 2 * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLAT_SOCFPGA_DEF_H 9 #define PLAT_SOCFPGA_DEF_H 10 11 #include <platform_def.h> 12 #include <lib/utils_def.h> 13 #include "n5x_system_manager.h" 14 15 /* Platform Setting */ 16 #define PLATFORM_MODEL PLAT_SOCFPGA_N5X 17 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 18 #define PLAT_PRIMARY_CPU 0 19 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 20 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT 21 22 /* FPGA config helpers */ 23 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 24 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 25 26 /* QSPI Setting */ 27 #define CAD_QSPIDATA_OFST 0xff900000 28 #define CAD_QSPI_OFFSET 0xff8d2000 29 30 /* Register Mapping */ 31 #define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000) 32 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 33 #define SOCFPGA_MMC_REG_BASE U(0xff808000) 34 #define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000) 35 #define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000) 36 #define SOCFPGA_ECC_QSPI_REG_BASE U(0xffa22000) 37 38 #define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000) 39 #define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100) 40 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200) 41 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) 42 43 44 /******************************************************************************* 45 * Platform memory map related constants 46 ******************************************************************************/ 47 #define DRAM_BASE (0x0) 48 #define DRAM_SIZE (0x80000000) 49 50 #define OCRAM_BASE (0xFFE00000) 51 #define OCRAM_SIZE (0x00040000) 52 53 #define MEM64_BASE (0x0100000000) 54 #define MEM64_SIZE (0x1F00000000) 55 56 #define DEVICE1_BASE (0x80000000) 57 #define DEVICE1_SIZE (0x60000000) 58 59 #define DEVICE2_BASE (0xF7000000) 60 #define DEVICE2_SIZE (0x08E00000) 61 62 #define DEVICE3_BASE (0xFFFC0000) 63 #define DEVICE3_SIZE (0x00008000) 64 65 #define DEVICE4_BASE (0x2000000000) 66 #define DEVICE4_SIZE (0x0100000000) 67 68 #define BL2_BASE (0xffe00000) 69 #define BL2_LIMIT (0xffe1b000) 70 71 #define BL31_BASE (0x1000) 72 #define BL31_LIMIT (0x81000) 73 74 /******************************************************************************* 75 * UART related constants 76 ******************************************************************************/ 77 #define PLAT_UART0_BASE (0xFFC02000) 78 #define PLAT_UART1_BASE (0xFFC02100) 79 80 /******************************************************************************* 81 * WDT related constants 82 ******************************************************************************/ 83 #define WDT_BASE (0xFFD00200) 84 85 /******************************************************************************* 86 * GIC related constants 87 ******************************************************************************/ 88 #define PLAT_GIC_BASE (0xFFFC0000) 89 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 90 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 91 #define PLAT_GICR_BASE 0 92 93 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 94 #define PLAT_HZ_CONVERT_TO_MHZ (1000000) 95 96 /******************************************************************************* 97 * SDMMC related pointer function 98 ******************************************************************************/ 99 #define SDMMC_READ_BLOCKS mmc_read_blocks 100 #define SDMMC_WRITE_BLOCKS mmc_write_blocks 101 102 /******************************************************************************* 103 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 104 * is done and HPS should trigger warm reset via RMR_EL3. 105 ******************************************************************************/ 106 #define L2_RESET_DONE_REG 0xFFD12218 107 108 /* Platform specific system counter */ 109 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 110 111 #endif /* PLAT_SOCFPGA_DEF_H */ 112