xref: /rk3399_ARM-atf/plat/intel/soc/common/socfpga_topology.c (revision d8820789ca2530e34ea4dff5d22bb6b7064d6737)
1*d8820789SHadi Asyrafi /*
2*d8820789SHadi Asyrafi  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*d8820789SHadi Asyrafi  *
4*d8820789SHadi Asyrafi  * SPDX-License-Identifier: BSD-3-Clause
5*d8820789SHadi Asyrafi  */
6*d8820789SHadi Asyrafi 
7*d8820789SHadi Asyrafi #include <arch.h>
8*d8820789SHadi Asyrafi #include <platform_def.h>
9*d8820789SHadi Asyrafi #include <lib/psci/psci.h>
10*d8820789SHadi Asyrafi 
11*d8820789SHadi Asyrafi static const unsigned char plat_power_domain_tree_desc[] = {1, 4};
12*d8820789SHadi Asyrafi 
13*d8820789SHadi Asyrafi /*******************************************************************************
14*d8820789SHadi Asyrafi  * This function returns the default topology tree information.
15*d8820789SHadi Asyrafi  ******************************************************************************/
16*d8820789SHadi Asyrafi const unsigned char *plat_get_power_domain_tree_desc(void)
17*d8820789SHadi Asyrafi {
18*d8820789SHadi Asyrafi 	return plat_power_domain_tree_desc;
19*d8820789SHadi Asyrafi }
20*d8820789SHadi Asyrafi 
21*d8820789SHadi Asyrafi /*******************************************************************************
22*d8820789SHadi Asyrafi  * This function implements a part of the critical interface between the psci
23*d8820789SHadi Asyrafi  * generic layer and the platform that allows the former to query the platform
24*d8820789SHadi Asyrafi  * to convert an MPIDR to a unique linear index. An error code (-1) is returned
25*d8820789SHadi Asyrafi  * in case the MPIDR is invalid.
26*d8820789SHadi Asyrafi  ******************************************************************************/
27*d8820789SHadi Asyrafi int plat_core_pos_by_mpidr(u_register_t mpidr)
28*d8820789SHadi Asyrafi {
29*d8820789SHadi Asyrafi 	unsigned int cluster_id, cpu_id;
30*d8820789SHadi Asyrafi 
31*d8820789SHadi Asyrafi 	mpidr &= MPIDR_AFFINITY_MASK;
32*d8820789SHadi Asyrafi 
33*d8820789SHadi Asyrafi 	if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
34*d8820789SHadi Asyrafi 		return -1;
35*d8820789SHadi Asyrafi 
36*d8820789SHadi Asyrafi 	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
37*d8820789SHadi Asyrafi 	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
38*d8820789SHadi Asyrafi 
39*d8820789SHadi Asyrafi 	if (cluster_id >= PLATFORM_CLUSTER_COUNT)
40*d8820789SHadi Asyrafi 		return -1;
41*d8820789SHadi Asyrafi 
42*d8820789SHadi Asyrafi 	/*
43*d8820789SHadi Asyrafi 	 * Validate cpu_id by checking whether it represents a CPU in
44*d8820789SHadi Asyrafi 	 * one of the two clusters present on the platform.
45*d8820789SHadi Asyrafi 	 */
46*d8820789SHadi Asyrafi 	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
47*d8820789SHadi Asyrafi 		return -1;
48*d8820789SHadi Asyrafi 
49*d8820789SHadi Asyrafi 	return (cpu_id + (cluster_id * 4));
50*d8820789SHadi Asyrafi }
51*d8820789SHadi Asyrafi 
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