1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/cadence/cdns_nand.h> 13 #include <drivers/cadence/cdns_sdmmc.h> 14 #include <drivers/io/io_block.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_fip.h> 17 #include <drivers/io/io_memmap.h> 18 #include <drivers/io/io_mtd.h> 19 #include <drivers/io/io_storage.h> 20 #include <drivers/mmc.h> 21 #include <drivers/partition/partition.h> 22 #include <lib/mmio.h> 23 #include <tools_share/firmware_image_package.h> 24 25 #include "drivers/sdmmc/sdmmc.h" 26 #include "socfpga_private.h" 27 #include "socfpga_ros.h" 28 29 30 #define PLAT_FIP_BASE (0) 31 #define PLAT_FIP_MAX_SIZE (0x1000000) 32 #define PLAT_MMC_DATA_BASE (0xffe3c000) 33 #define PLAT_MMC_DATA_SIZE (0x2000) 34 35 static const io_dev_connector_t *fip_dev_con; 36 static const io_dev_connector_t *boot_dev_con; 37 38 static io_mtd_dev_spec_t nand_dev_spec; 39 40 static uintptr_t fip_dev_handle; 41 static uintptr_t boot_dev_handle; 42 43 static const io_uuid_spec_t bl2_uuid_spec = { 44 .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, 45 }; 46 47 static const io_uuid_spec_t bl31_uuid_spec = { 48 .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, 49 }; 50 51 static const io_uuid_spec_t bl33_uuid_spec = { 52 .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, 53 }; 54 55 uintptr_t a2_lba_offset; 56 const char a2[] = {0xa2, 0x0}; 57 58 static const io_block_spec_t gpt_block_spec = { 59 .offset = 0, 60 .length = MMC_BLOCK_SIZE 61 }; 62 63 static int check_fip(const uintptr_t spec); 64 static int check_dev(const uintptr_t spec); 65 66 static io_block_dev_spec_t boot_dev_spec; 67 static int (*register_io_dev)(const io_dev_connector_t **); 68 69 static io_block_spec_t fip_spec = { 70 .offset = PLAT_FIP_BASE, 71 .length = PLAT_FIP_MAX_SIZE, 72 }; 73 74 struct plat_io_policy { 75 uintptr_t *dev_handle; 76 uintptr_t image_spec; 77 int (*check)(const uintptr_t spec); 78 }; 79 80 static const struct plat_io_policy policies[] = { 81 [FIP_IMAGE_ID] = { 82 &boot_dev_handle, 83 (uintptr_t)&fip_spec, 84 check_dev 85 }, 86 [BL2_IMAGE_ID] = { 87 &fip_dev_handle, 88 (uintptr_t)&bl2_uuid_spec, 89 check_fip 90 }, 91 [BL31_IMAGE_ID] = { 92 &fip_dev_handle, 93 (uintptr_t)&bl31_uuid_spec, 94 check_fip 95 }, 96 [BL33_IMAGE_ID] = { 97 &fip_dev_handle, 98 (uintptr_t) &bl33_uuid_spec, 99 check_fip 100 }, 101 [GPT_IMAGE_ID] = { 102 &boot_dev_handle, 103 (uintptr_t) &gpt_block_spec, 104 check_dev 105 }, 106 }; 107 108 static int check_dev(const uintptr_t spec) 109 { 110 int result; 111 uintptr_t local_handle; 112 113 result = io_dev_init(boot_dev_handle, (uintptr_t)NULL); 114 if (result == 0) { 115 result = io_open(boot_dev_handle, spec, &local_handle); 116 if (result == 0) 117 io_close(local_handle); 118 } 119 return result; 120 } 121 122 static int check_fip(const uintptr_t spec) 123 { 124 int result; 125 uintptr_t local_image_handle; 126 127 result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 128 if (result == 0) { 129 result = io_open(fip_dev_handle, spec, &local_image_handle); 130 if (result == 0) 131 io_close(local_image_handle); 132 } 133 return result; 134 } 135 136 void socfpga_io_setup(int boot_source, unsigned long offset) 137 { 138 int result; 139 fip_spec.offset = offset; 140 141 switch (boot_source) { 142 case BOOT_SOURCE_SDMMC: 143 register_io_dev = ®ister_io_dev_block; 144 boot_dev_spec.buffer.offset = PLAT_MMC_DATA_BASE; 145 boot_dev_spec.buffer.length = SOCFPGA_MMC_BLOCK_SIZE; 146 boot_dev_spec.ops.read = SDMMC_READ_BLOCKS; 147 boot_dev_spec.ops.write = SDMMC_WRITE_BLOCKS; 148 boot_dev_spec.block_size = MMC_BLOCK_SIZE; 149 break; 150 151 case BOOT_SOURCE_QSPI: 152 register_io_dev = ®ister_io_dev_memmap; 153 break; 154 155 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 156 case BOOT_SOURCE_NAND: 157 register_io_dev = ®ister_io_dev_mtd; 158 nand_dev_spec.ops.init = cdns_nand_init_mtd; 159 nand_dev_spec.ops.read = cdns_nand_read; 160 nand_dev_spec.ops.write = NULL; 161 break; 162 #endif 163 164 default: 165 ERROR("Unsupported boot source\n"); 166 panic(); 167 break; 168 } 169 170 result = (*register_io_dev)(&boot_dev_con); 171 assert(result == 0); 172 173 result = register_io_dev_fip(&fip_dev_con); 174 assert(result == 0); 175 176 if (boot_source == BOOT_SOURCE_NAND) { 177 result = io_dev_open(boot_dev_con, (uintptr_t)&nand_dev_spec, 178 &boot_dev_handle); 179 } else { 180 result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec, 181 &boot_dev_handle); 182 } 183 assert(result == 0); 184 185 result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); 186 assert(result == 0); 187 188 if (boot_source == BOOT_SOURCE_SDMMC) { 189 partition_init(GPT_IMAGE_ID); 190 fip_spec.offset = get_partition_entry(a2)->start; 191 } 192 193 (void)result; 194 } 195 196 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 197 uintptr_t *image_spec) 198 { 199 int result; 200 const struct plat_io_policy *policy; 201 202 assert(image_id < ARRAY_SIZE(policies)); 203 204 policy = &policies[image_id]; 205 result = policy->check(policy->image_spec); 206 assert(result == 0); 207 208 *image_spec = policy->image_spec; 209 *dev_handle = *(policy->dev_handle); 210 211 return result; 212 } 213