1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_plat_def.h" 16 #include "socfpga_reset_manager.h" 17 #include "socfpga_sip_svc.h" 18 #include "socfpga_system_manager.h" 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static config_type request_type = NO_REQUEST; 24 static int current_block, current_buffer; 25 static int read_block, max_blocks; 26 static uint32_t send_id, rcv_id; 27 static uint32_t bytes_per_block, blocks_submitted; 28 static bool bridge_disable; 29 30 /* RSU static variables */ 31 static uint32_t rsu_dcmf_ver[4] = {0}; 32 static uint16_t rsu_dcmf_stat[4] = {0}; 33 static uint32_t rsu_max_retry; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(void) 93 { 94 uint32_t ret; 95 96 switch (request_type) { 97 case RECONFIGURATION: 98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 99 true); 100 break; 101 case BITSTREAM_AUTH: 102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 103 false); 104 break; 105 default: 106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 107 false); 108 break; 109 } 110 111 if (ret != 0U) { 112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 113 return INTEL_SIP_SMC_STATUS_BUSY; 114 } else { 115 request_type = NO_REQUEST; 116 return INTEL_SIP_SMC_STATUS_ERROR; 117 } 118 } 119 120 if (bridge_disable != 0U) { 121 socfpga_bridges_enable(~0); /* Enable bridge */ 122 bridge_disable = false; 123 } 124 request_type = NO_REQUEST; 125 126 return INTEL_SIP_SMC_STATUS_OK; 127 } 128 129 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 130 { 131 int i; 132 133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 134 if (fpga_config_buffers[i].block_number == current_block) { 135 fpga_config_buffers[i].subblocks_sent--; 136 if (fpga_config_buffers[i].subblocks_sent == 0 137 && fpga_config_buffers[i].size <= 138 fpga_config_buffers[i].size_written) { 139 fpga_config_buffers[i].write_requested = 0; 140 current_block++; 141 *buffer_addr_completed = 142 fpga_config_buffers[i].addr; 143 return 0; 144 } 145 } 146 } 147 148 return -1; 149 } 150 151 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 152 uint32_t *count, uint32_t *job_id) 153 { 154 uint32_t resp[5]; 155 unsigned int resp_len = ARRAY_SIZE(resp); 156 int status = INTEL_SIP_SMC_STATUS_OK; 157 int all_completed = 1; 158 *count = 0; 159 160 while (*count < 3) { 161 162 status = mailbox_read_response(job_id, 163 resp, &resp_len); 164 165 if (status < 0) { 166 break; 167 } 168 169 max_blocks++; 170 171 if (mark_last_buffer_xfer_completed( 172 &completed_addr[*count]) == 0) { 173 *count = *count + 1; 174 } else { 175 break; 176 } 177 } 178 179 if (*count <= 0) { 180 if (status != MBOX_NO_RESPONSE && 181 status != MBOX_TIMEOUT && resp_len != 0) { 182 mailbox_clear_response(); 183 request_type = NO_REQUEST; 184 return INTEL_SIP_SMC_STATUS_ERROR; 185 } 186 187 *count = 0; 188 } 189 190 intel_fpga_sdm_write_all(); 191 192 if (*count > 0) { 193 status = INTEL_SIP_SMC_STATUS_OK; 194 } else if (*count == 0) { 195 status = INTEL_SIP_SMC_STATUS_BUSY; 196 } 197 198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 199 if (fpga_config_buffers[i].write_requested != 0) { 200 all_completed = 0; 201 break; 202 } 203 } 204 205 if (all_completed == 1) { 206 return INTEL_SIP_SMC_STATUS_OK; 207 } 208 209 return status; 210 } 211 212 static int intel_fpga_config_start(uint32_t flag) 213 { 214 uint32_t argument = 0x1; 215 uint32_t response[3]; 216 int status = 0; 217 unsigned int size = 0; 218 unsigned int resp_len = ARRAY_SIZE(response); 219 220 request_type = RECONFIGURATION; 221 222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 223 bridge_disable = true; 224 } 225 226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 227 size = 1; 228 bridge_disable = false; 229 request_type = BITSTREAM_AUTH; 230 } 231 232 mailbox_clear_response(); 233 234 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 235 CMD_CASUAL, NULL, NULL); 236 237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 238 CMD_CASUAL, response, &resp_len); 239 240 if (status < 0) { 241 bridge_disable = false; 242 request_type = NO_REQUEST; 243 return INTEL_SIP_SMC_STATUS_ERROR; 244 } 245 246 max_blocks = response[0]; 247 bytes_per_block = response[1]; 248 249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 250 fpga_config_buffers[i].size = 0; 251 fpga_config_buffers[i].size_written = 0; 252 fpga_config_buffers[i].addr = 0; 253 fpga_config_buffers[i].write_requested = 0; 254 fpga_config_buffers[i].block_number = 0; 255 fpga_config_buffers[i].subblocks_sent = 0; 256 } 257 258 blocks_submitted = 0; 259 current_block = 0; 260 read_block = 0; 261 current_buffer = 0; 262 263 /* Disable bridge on full reconfiguration */ 264 if (bridge_disable) { 265 socfpga_bridges_disable(~0); 266 } 267 268 return INTEL_SIP_SMC_STATUS_OK; 269 } 270 271 static bool is_fpga_config_buffer_full(void) 272 { 273 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 274 if (!fpga_config_buffers[i].write_requested) { 275 return false; 276 } 277 } 278 return true; 279 } 280 281 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 282 { 283 if (!addr && !size) { 284 return true; 285 } 286 if (size > (UINT64_MAX - addr)) { 287 return false; 288 } 289 if (addr < BL31_LIMIT) { 290 return false; 291 } 292 if (addr + size > DRAM_BASE + DRAM_SIZE) { 293 return false; 294 } 295 296 return true; 297 } 298 299 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 300 { 301 int i; 302 303 intel_fpga_sdm_write_all(); 304 305 if (!is_address_in_ddr_range(mem, size) || 306 is_fpga_config_buffer_full()) { 307 return INTEL_SIP_SMC_STATUS_REJECTED; 308 } 309 310 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 311 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 312 313 if (!fpga_config_buffers[j].write_requested) { 314 fpga_config_buffers[j].addr = mem; 315 fpga_config_buffers[j].size = size; 316 fpga_config_buffers[j].size_written = 0; 317 fpga_config_buffers[j].write_requested = 1; 318 fpga_config_buffers[j].block_number = 319 blocks_submitted++; 320 fpga_config_buffers[j].subblocks_sent = 0; 321 break; 322 } 323 } 324 325 if (is_fpga_config_buffer_full()) { 326 return INTEL_SIP_SMC_STATUS_BUSY; 327 } 328 329 return INTEL_SIP_SMC_STATUS_OK; 330 } 331 332 static int is_out_of_sec_range(uint64_t reg_addr) 333 { 334 #if DEBUG 335 return 0; 336 #endif 337 338 switch (reg_addr) { 339 case(0xF8011100): /* ECCCTRL1 */ 340 case(0xF8011104): /* ECCCTRL2 */ 341 case(0xF8011110): /* ERRINTEN */ 342 case(0xF8011114): /* ERRINTENS */ 343 case(0xF8011118): /* ERRINTENR */ 344 case(0xF801111C): /* INTMODE */ 345 case(0xF8011120): /* INTSTAT */ 346 case(0xF8011124): /* DIAGINTTEST */ 347 case(0xF801112C): /* DERRADDRA */ 348 case(0xFA000000): /* SMMU SCR0 */ 349 case(0xFA000004): /* SMMU SCR1 */ 350 case(0xFA000400): /* SMMU NSCR0 */ 351 case(0xFA004000): /* SMMU SSD0_REG */ 352 case(0xFA000820): /* SMMU SMR8 */ 353 case(0xFA000c20): /* SMMU SCR8 */ 354 case(0xFA028000): /* SMMU CB8_SCTRL */ 355 case(0xFA001020): /* SMMU CBAR8 */ 356 case(0xFA028030): /* SMMU TCR_LPAE */ 357 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 358 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 359 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 360 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 361 case(0xFA028010): /* SMMU_CB8)TCR2 */ 362 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 363 case(0xFA001820): /* SMMU_CBA2R8 */ 364 case(0xFA000074): /* SMMU_STLBGSTATUS */ 365 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 366 case(0xFA000060): /* SMMU_STLBIALL */ 367 case(0xFA000070): /* SMMU_STLBGSYNC */ 368 case(0xFA028618): /* CB8_TLBALL */ 369 case(0xFA0287F0): /* CB8_TLBSYNC */ 370 case(0xFFD12028): /* SDMMCGRP_CTRL */ 371 case(0xFFD12044): /* EMAC0 */ 372 case(0xFFD12048): /* EMAC1 */ 373 case(0xFFD1204C): /* EMAC2 */ 374 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 375 case(0xFFD12094): /* ECC_INT_MASK_SET */ 376 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 377 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 378 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 379 case(0xFFD120C0): /* NOC_TIMEOUT */ 380 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 381 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 382 case(0xFFD120D0): /* NOC_IDLEACK */ 383 case(0xFFD120D4): /* NOC_IDLESTATUS */ 384 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 385 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 386 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 387 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 388 return 0; 389 390 default: 391 break; 392 } 393 394 return -1; 395 } 396 397 /* Secure register access */ 398 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 399 { 400 if (is_out_of_sec_range(reg_addr)) { 401 return INTEL_SIP_SMC_STATUS_ERROR; 402 } 403 404 *retval = mmio_read_32(reg_addr); 405 406 return INTEL_SIP_SMC_STATUS_OK; 407 } 408 409 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 410 uint32_t *retval) 411 { 412 if (is_out_of_sec_range(reg_addr)) { 413 return INTEL_SIP_SMC_STATUS_ERROR; 414 } 415 416 mmio_write_32(reg_addr, val); 417 418 return intel_secure_reg_read(reg_addr, retval); 419 } 420 421 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 422 uint32_t val, uint32_t *retval) 423 { 424 if (!intel_secure_reg_read(reg_addr, retval)) { 425 *retval &= ~mask; 426 *retval |= val & mask; 427 return intel_secure_reg_write(reg_addr, *retval, retval); 428 } 429 430 return INTEL_SIP_SMC_STATUS_ERROR; 431 } 432 433 /* Intel Remote System Update (RSU) services */ 434 uint64_t intel_rsu_update_address; 435 436 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 437 { 438 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 439 return INTEL_SIP_SMC_RSU_ERROR; 440 } 441 442 return INTEL_SIP_SMC_STATUS_OK; 443 } 444 445 static uint32_t intel_rsu_update(uint64_t update_address) 446 { 447 if (update_address > SIZE_MAX) { 448 return INTEL_SIP_SMC_STATUS_REJECTED; 449 } 450 451 intel_rsu_update_address = update_address; 452 return INTEL_SIP_SMC_STATUS_OK; 453 } 454 455 static uint32_t intel_rsu_notify(uint32_t execution_stage) 456 { 457 if (mailbox_hps_stage_notify(execution_stage) < 0) { 458 return INTEL_SIP_SMC_RSU_ERROR; 459 } 460 461 return INTEL_SIP_SMC_STATUS_OK; 462 } 463 464 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 465 uint32_t *ret_stat) 466 { 467 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 468 return INTEL_SIP_SMC_RSU_ERROR; 469 } 470 471 *ret_stat = respbuf[8]; 472 return INTEL_SIP_SMC_STATUS_OK; 473 } 474 475 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 476 uint64_t dcmf_ver_3_2) 477 { 478 rsu_dcmf_ver[0] = dcmf_ver_1_0; 479 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 480 rsu_dcmf_ver[2] = dcmf_ver_3_2; 481 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 482 483 return INTEL_SIP_SMC_STATUS_OK; 484 } 485 486 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 487 { 488 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 489 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 490 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 491 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 492 493 return INTEL_SIP_SMC_STATUS_OK; 494 } 495 496 /* Intel HWMON services */ 497 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 498 { 499 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 500 return INTEL_SIP_SMC_STATUS_ERROR; 501 } 502 503 return INTEL_SIP_SMC_STATUS_OK; 504 } 505 506 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 507 { 508 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 509 return INTEL_SIP_SMC_STATUS_ERROR; 510 } 511 512 return INTEL_SIP_SMC_STATUS_OK; 513 } 514 515 /* Mailbox services */ 516 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 517 { 518 int status; 519 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 520 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 521 522 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 523 CMD_CASUAL, resp_data, &resp_len); 524 525 if (status < 0) { 526 return INTEL_SIP_SMC_STATUS_ERROR; 527 } 528 529 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 530 return INTEL_SIP_SMC_STATUS_ERROR; 531 } 532 533 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 534 535 return INTEL_SIP_SMC_STATUS_OK; 536 } 537 538 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 539 unsigned int len, uint32_t urgent, uint64_t response, 540 unsigned int resp_len, int *mbox_status, 541 unsigned int *len_in_resp) 542 { 543 *len_in_resp = 0; 544 *mbox_status = GENERIC_RESPONSE_ERROR; 545 546 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 547 return INTEL_SIP_SMC_STATUS_REJECTED; 548 } 549 550 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 551 (uint32_t *) response, &resp_len); 552 553 if (status < 0) { 554 *mbox_status = -status; 555 return INTEL_SIP_SMC_STATUS_ERROR; 556 } 557 558 *mbox_status = 0; 559 *len_in_resp = resp_len; 560 561 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 562 563 return INTEL_SIP_SMC_STATUS_OK; 564 } 565 566 static int intel_smc_get_usercode(uint32_t *user_code) 567 { 568 int status; 569 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 570 571 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 572 0U, CMD_CASUAL, user_code, &resp_len); 573 574 if (status < 0) { 575 return INTEL_SIP_SMC_STATUS_ERROR; 576 } 577 578 return INTEL_SIP_SMC_STATUS_OK; 579 } 580 581 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 582 uint32_t mode, uint32_t *job_id, 583 uint32_t *ret_size, uint32_t *mbox_error) 584 { 585 int status = 0; 586 uint32_t resp_len = size / MBOX_WORD_BYTE; 587 588 if (resp_len > MBOX_DATA_MAX_LEN) { 589 return INTEL_SIP_SMC_STATUS_REJECTED; 590 } 591 592 if (!is_address_in_ddr_range(addr, size)) { 593 return INTEL_SIP_SMC_STATUS_REJECTED; 594 } 595 596 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 597 status = mailbox_read_response_async(job_id, 598 NULL, (uint32_t *) addr, &resp_len, 0); 599 } else { 600 status = mailbox_read_response(job_id, 601 (uint32_t *) addr, &resp_len); 602 603 if (status == MBOX_NO_RESPONSE) { 604 status = MBOX_BUSY; 605 } 606 } 607 608 if (status == MBOX_NO_RESPONSE) { 609 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 610 } 611 612 if (status == MBOX_BUSY) { 613 return INTEL_SIP_SMC_STATUS_BUSY; 614 } 615 616 *ret_size = resp_len * MBOX_WORD_BYTE; 617 flush_dcache_range(addr, *ret_size); 618 619 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 620 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 621 *mbox_error = -status; 622 } else if (status != MBOX_RET_OK) { 623 *mbox_error = -status; 624 return INTEL_SIP_SMC_STATUS_ERROR; 625 } 626 627 return INTEL_SIP_SMC_STATUS_OK; 628 } 629 630 /* Miscellaneous HPS services */ 631 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 632 { 633 int status = 0; 634 635 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 636 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 637 status = socfpga_bridges_enable((uint32_t)mask); 638 } else { 639 status = socfpga_bridges_enable(~0); 640 } 641 } else { 642 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 643 status = socfpga_bridges_disable((uint32_t)mask); 644 } else { 645 status = socfpga_bridges_disable(~0); 646 } 647 } 648 649 if (status < 0) { 650 return INTEL_SIP_SMC_STATUS_ERROR; 651 } 652 653 return INTEL_SIP_SMC_STATUS_OK; 654 } 655 656 /* SDM SEU Error services */ 657 static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz) 658 { 659 if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) { 660 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 661 } 662 663 return INTEL_SIP_SMC_STATUS_OK; 664 } 665 666 /* 667 * This function is responsible for handling all SiP calls from the NS world 668 */ 669 670 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 671 u_register_t x1, 672 u_register_t x2, 673 u_register_t x3, 674 u_register_t x4, 675 void *cookie, 676 void *handle, 677 u_register_t flags) 678 { 679 uint32_t retval = 0, completed_addr[3]; 680 uint32_t retval2 = 0; 681 uint32_t mbox_error = 0; 682 uint64_t retval64, rsu_respbuf[9], seu_respbuf[3]; 683 int status = INTEL_SIP_SMC_STATUS_OK; 684 int mbox_status; 685 unsigned int len_in_resp; 686 u_register_t x5, x6, x7; 687 688 switch (smc_fid) { 689 case SIP_SVC_UID: 690 /* Return UID to the caller */ 691 SMC_UUID_RET(handle, intl_svc_uid); 692 693 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 694 status = intel_mailbox_fpga_config_isdone(); 695 SMC_RET4(handle, status, 0, 0, 0); 696 697 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 698 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 699 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 700 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 701 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 702 703 case INTEL_SIP_SMC_FPGA_CONFIG_START: 704 status = intel_fpga_config_start(x1); 705 SMC_RET4(handle, status, 0, 0, 0); 706 707 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 708 status = intel_fpga_config_write(x1, x2); 709 SMC_RET4(handle, status, 0, 0, 0); 710 711 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 712 status = intel_fpga_config_completed_write(completed_addr, 713 &retval, &rcv_id); 714 switch (retval) { 715 case 1: 716 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 717 completed_addr[0], 0, 0); 718 719 case 2: 720 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 721 completed_addr[0], 722 completed_addr[1], 0); 723 724 case 3: 725 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 726 completed_addr[0], 727 completed_addr[1], 728 completed_addr[2]); 729 730 case 0: 731 SMC_RET4(handle, status, 0, 0, 0); 732 733 default: 734 mailbox_clear_response(); 735 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 736 } 737 738 case INTEL_SIP_SMC_REG_READ: 739 status = intel_secure_reg_read(x1, &retval); 740 SMC_RET3(handle, status, retval, x1); 741 742 case INTEL_SIP_SMC_REG_WRITE: 743 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 744 SMC_RET3(handle, status, retval, x1); 745 746 case INTEL_SIP_SMC_REG_UPDATE: 747 status = intel_secure_reg_update(x1, (uint32_t)x2, 748 (uint32_t)x3, &retval); 749 SMC_RET3(handle, status, retval, x1); 750 751 case INTEL_SIP_SMC_RSU_STATUS: 752 status = intel_rsu_status(rsu_respbuf, 753 ARRAY_SIZE(rsu_respbuf)); 754 if (status) { 755 SMC_RET1(handle, status); 756 } else { 757 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 758 rsu_respbuf[2], rsu_respbuf[3]); 759 } 760 761 case INTEL_SIP_SMC_RSU_UPDATE: 762 status = intel_rsu_update(x1); 763 SMC_RET1(handle, status); 764 765 case INTEL_SIP_SMC_RSU_NOTIFY: 766 status = intel_rsu_notify(x1); 767 SMC_RET1(handle, status); 768 769 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 770 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 771 ARRAY_SIZE(rsu_respbuf), &retval); 772 if (status) { 773 SMC_RET1(handle, status); 774 } else { 775 SMC_RET2(handle, status, retval); 776 } 777 778 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 779 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 780 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 781 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 782 783 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 784 status = intel_rsu_copy_dcmf_version(x1, x2); 785 SMC_RET1(handle, status); 786 787 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 788 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 789 ((uint64_t)rsu_dcmf_stat[3] << 48) | 790 ((uint64_t)rsu_dcmf_stat[2] << 32) | 791 ((uint64_t)rsu_dcmf_stat[1] << 16) | 792 rsu_dcmf_stat[0]); 793 794 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 795 status = intel_rsu_copy_dcmf_status(x1); 796 SMC_RET1(handle, status); 797 798 case INTEL_SIP_SMC_RSU_MAX_RETRY: 799 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 800 801 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 802 rsu_max_retry = x1; 803 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 804 805 case INTEL_SIP_SMC_ECC_DBE: 806 status = intel_ecc_dbe_notification(x1); 807 SMC_RET1(handle, status); 808 809 case INTEL_SIP_SMC_SERVICE_COMPLETED: 810 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 811 &len_in_resp, &mbox_error); 812 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 813 814 case INTEL_SIP_SMC_FIRMWARE_VERSION: 815 status = intel_smc_fw_version(&retval); 816 SMC_RET2(handle, status, retval); 817 818 case INTEL_SIP_SMC_MBOX_SEND_CMD: 819 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 820 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 821 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 822 &mbox_status, &len_in_resp); 823 SMC_RET3(handle, status, mbox_status, len_in_resp); 824 825 case INTEL_SIP_SMC_GET_USERCODE: 826 status = intel_smc_get_usercode(&retval); 827 SMC_RET2(handle, status, retval); 828 829 case INTEL_SIP_SMC_FCS_CRYPTION: 830 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 831 832 if (x1 == FCS_MODE_DECRYPT) { 833 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 834 } else if (x1 == FCS_MODE_ENCRYPT) { 835 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 836 } else { 837 status = INTEL_SIP_SMC_STATUS_REJECTED; 838 } 839 840 SMC_RET3(handle, status, x4, x5); 841 842 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 843 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 844 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 845 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 846 847 if (x3 == FCS_MODE_DECRYPT) { 848 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 849 (uint32_t *) &x7, &mbox_error); 850 } else if (x3 == FCS_MODE_ENCRYPT) { 851 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 852 (uint32_t *) &x7, &mbox_error); 853 } else { 854 status = INTEL_SIP_SMC_STATUS_REJECTED; 855 } 856 857 SMC_RET4(handle, status, mbox_error, x6, x7); 858 859 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 860 status = intel_fcs_random_number_gen(x1, &retval64, 861 &mbox_error); 862 SMC_RET4(handle, status, mbox_error, x1, retval64); 863 864 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 865 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 866 &send_id); 867 SMC_RET1(handle, status); 868 869 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 870 status = intel_fcs_send_cert(x1, x2, &send_id); 871 SMC_RET1(handle, status); 872 873 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 874 status = intel_fcs_get_provision_data(&send_id); 875 SMC_RET1(handle, status); 876 877 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 878 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 879 &mbox_error); 880 SMC_RET2(handle, status, mbox_error); 881 882 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 883 status = intel_hps_set_bridges(x1, x2); 884 SMC_RET1(handle, status); 885 886 case INTEL_SIP_SMC_HWMON_READTEMP: 887 status = intel_hwmon_readtemp(x1, &retval); 888 SMC_RET2(handle, status, retval); 889 890 case INTEL_SIP_SMC_HWMON_READVOLT: 891 status = intel_hwmon_readvolt(x1, &retval); 892 SMC_RET2(handle, status, retval); 893 894 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 895 status = intel_fcs_sigma_teardown(x1, &mbox_error); 896 SMC_RET2(handle, status, mbox_error); 897 898 case INTEL_SIP_SMC_FCS_CHIP_ID: 899 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 900 SMC_RET4(handle, status, mbox_error, retval, retval2); 901 902 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 903 status = intel_fcs_attestation_subkey(x1, x2, x3, 904 (uint32_t *) &x4, &mbox_error); 905 SMC_RET4(handle, status, mbox_error, x3, x4); 906 907 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 908 status = intel_fcs_get_measurement(x1, x2, x3, 909 (uint32_t *) &x4, &mbox_error); 910 SMC_RET4(handle, status, mbox_error, x3, x4); 911 912 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 913 status = intel_fcs_get_attestation_cert(x1, x2, 914 (uint32_t *) &x3, &mbox_error); 915 SMC_RET4(handle, status, mbox_error, x2, x3); 916 917 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 918 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 919 SMC_RET2(handle, status, mbox_error); 920 921 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 922 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 923 SMC_RET3(handle, status, mbox_error, retval); 924 925 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 926 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 927 SMC_RET2(handle, status, mbox_error); 928 929 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 930 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 931 SMC_RET1(handle, status); 932 933 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 934 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 935 (uint32_t *) &x4, &mbox_error); 936 SMC_RET4(handle, status, mbox_error, x3, x4); 937 938 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 939 status = intel_fcs_remove_crypto_service_key(x1, x2, 940 &mbox_error); 941 SMC_RET2(handle, status, mbox_error); 942 943 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 944 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 945 (uint32_t *) &x4, &mbox_error); 946 SMC_RET4(handle, status, mbox_error, x3, x4); 947 948 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 949 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 950 status = intel_fcs_get_digest_init(x1, x2, x3, 951 x4, x5, &mbox_error); 952 SMC_RET2(handle, status, mbox_error); 953 954 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 955 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 956 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 957 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 958 x4, x5, (uint32_t *) &x6, false, 959 &mbox_error); 960 SMC_RET4(handle, status, mbox_error, x5, x6); 961 962 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 963 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 964 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 965 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 966 x4, x5, (uint32_t *) &x6, true, 967 &mbox_error); 968 SMC_RET4(handle, status, mbox_error, x5, x6); 969 970 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 971 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 972 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 973 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 974 x4, x5, (uint32_t *) &x6, false, 975 &mbox_error, &send_id); 976 SMC_RET4(handle, status, mbox_error, x5, x6); 977 978 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 979 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 980 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 981 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 982 x4, x5, (uint32_t *) &x6, true, 983 &mbox_error, &send_id); 984 SMC_RET4(handle, status, mbox_error, x5, x6); 985 986 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 987 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 988 status = intel_fcs_mac_verify_init(x1, x2, x3, 989 x4, x5, &mbox_error); 990 SMC_RET2(handle, status, mbox_error); 991 992 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 993 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 994 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 995 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 996 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 997 x4, x5, (uint32_t *) &x6, x7, 998 false, &mbox_error); 999 SMC_RET4(handle, status, mbox_error, x5, x6); 1000 1001 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1002 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1003 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1004 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1005 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1006 x4, x5, (uint32_t *) &x6, x7, 1007 true, &mbox_error); 1008 SMC_RET4(handle, status, mbox_error, x5, x6); 1009 1010 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1011 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1012 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1013 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1014 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1015 x4, x5, (uint32_t *) &x6, x7, 1016 false, &mbox_error, &send_id); 1017 SMC_RET4(handle, status, mbox_error, x5, x6); 1018 1019 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1020 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1021 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1022 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1023 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1024 x4, x5, (uint32_t *) &x6, x7, 1025 true, &mbox_error, &send_id); 1026 SMC_RET4(handle, status, mbox_error, x5, x6); 1027 1028 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1029 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1030 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1031 x4, x5, &mbox_error); 1032 SMC_RET2(handle, status, mbox_error); 1033 1034 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1035 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1036 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1037 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1038 x3, x4, x5, (uint32_t *) &x6, false, 1039 &mbox_error); 1040 SMC_RET4(handle, status, mbox_error, x5, x6); 1041 1042 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1043 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1044 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1045 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1046 x3, x4, x5, (uint32_t *) &x6, true, 1047 &mbox_error); 1048 SMC_RET4(handle, status, mbox_error, x5, x6); 1049 1050 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1051 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1052 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1053 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1054 x2, x3, x4, x5, (uint32_t *) &x6, false, 1055 &mbox_error, &send_id); 1056 SMC_RET4(handle, status, mbox_error, x5, x6); 1057 1058 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1059 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1060 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1061 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1062 x2, x3, x4, x5, (uint32_t *) &x6, true, 1063 &mbox_error, &send_id); 1064 SMC_RET4(handle, status, mbox_error, x5, x6); 1065 1066 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1067 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1068 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1069 x4, x5, &mbox_error); 1070 SMC_RET2(handle, status, mbox_error); 1071 1072 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1073 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1074 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1075 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1076 x4, x5, (uint32_t *) &x6, &mbox_error); 1077 SMC_RET4(handle, status, mbox_error, x5, x6); 1078 1079 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1080 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1081 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1082 x4, x5, &mbox_error); 1083 SMC_RET2(handle, status, mbox_error); 1084 1085 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1086 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1087 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1088 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1089 x4, x5, (uint32_t *) &x6, &mbox_error); 1090 SMC_RET4(handle, status, mbox_error, x5, x6); 1091 1092 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1093 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1094 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1095 x4, x5, &mbox_error); 1096 SMC_RET2(handle, status, mbox_error); 1097 1098 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1099 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1100 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1101 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1102 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1103 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1104 x7, false, &mbox_error); 1105 SMC_RET4(handle, status, mbox_error, x5, x6); 1106 1107 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1108 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1109 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1110 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1111 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1112 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1113 x7, false, &mbox_error, &send_id); 1114 SMC_RET4(handle, status, mbox_error, x5, x6); 1115 1116 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1117 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1118 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1119 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1120 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1121 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1122 x7, true, &mbox_error, &send_id); 1123 SMC_RET4(handle, status, mbox_error, x5, x6); 1124 1125 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1126 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1127 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1128 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1129 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1130 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1131 x7, true, &mbox_error); 1132 SMC_RET4(handle, status, mbox_error, x5, x6); 1133 1134 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1135 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1136 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1137 x4, x5, &mbox_error); 1138 SMC_RET2(handle, status, mbox_error); 1139 1140 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1141 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1142 (uint32_t *) &x4, &mbox_error); 1143 SMC_RET4(handle, status, mbox_error, x3, x4); 1144 1145 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1146 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1147 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1148 x4, x5, &mbox_error); 1149 SMC_RET2(handle, status, mbox_error); 1150 1151 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1152 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1153 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1154 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1155 x4, x5, (uint32_t *) &x6, &mbox_error); 1156 SMC_RET4(handle, status, mbox_error, x5, x6); 1157 1158 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1159 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1160 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1161 &mbox_error); 1162 SMC_RET2(handle, status, mbox_error); 1163 1164 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1165 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1166 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1167 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1168 x5, x6, false, &send_id); 1169 SMC_RET1(handle, status); 1170 1171 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1172 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1173 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1174 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1175 x5, x6, true, &send_id); 1176 SMC_RET1(handle, status); 1177 1178 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1179 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1180 &mbox_error); 1181 SMC_RET4(handle, status, mbox_error, x1, retval64); 1182 1183 case INTEL_SIP_SMC_SVC_VERSION: 1184 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1185 SIP_SVC_VERSION_MAJOR, 1186 SIP_SVC_VERSION_MINOR); 1187 1188 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1189 status = intel_sdm_seu_err_read(seu_respbuf, 1190 ARRAY_SIZE(seu_respbuf)); 1191 if (status) { 1192 SMC_RET1(handle, status); 1193 } else { 1194 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1195 } 1196 1197 default: 1198 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1199 cookie, handle, flags); 1200 } 1201 } 1202 1203 uintptr_t sip_smc_handler(uint32_t smc_fid, 1204 u_register_t x1, 1205 u_register_t x2, 1206 u_register_t x3, 1207 u_register_t x4, 1208 void *cookie, 1209 void *handle, 1210 u_register_t flags) 1211 { 1212 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1213 1214 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1215 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1216 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1217 cookie, handle, flags); 1218 } else { 1219 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1220 cookie, handle, flags); 1221 } 1222 } 1223 1224 DECLARE_RT_SVC( 1225 socfpga_sip_svc, 1226 OEN_SIP_START, 1227 OEN_SIP_END, 1228 SMC_TYPE_FAST, 1229 NULL, 1230 sip_smc_handler 1231 ); 1232 1233 DECLARE_RT_SVC( 1234 socfpga_sip_svc_std, 1235 OEN_SIP_START, 1236 OEN_SIP_END, 1237 SMC_TYPE_YIELD, 1238 NULL, 1239 sip_smc_handler 1240 ); 1241